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| ? 1994 microchip technology inc. ds00575a-page 1 ieee 754 compliant floating-point routines 5 AN575 ieee 754 compliant floating-point routines 5-11 introduction this application note presents an implementation of the following floating point math routines for the pic16/17 microcontroller family: intxx( a ) float to integer conversion floxx( a ) integer to float conversion nrmxx( a ) normalize fpaxx( a , b ) add/subtract fpmxx( a , b ) multiply fpdxx( a , b ) divide routines for the pic16/17 families are provided in a modified ieee754 32 bit format together with versions in 24-bit truncated format. floating point arithmetic although fixed point arithmetic can usually be employed in many numerical problems through the use of proper scaling techniques, this approach can become compli- cated and sometimes result in less efficient code than is possible using floating point methods [1] . floating point arithmetic is essentially equivalent to arithmetic in scien- tific notation relative to a particular base or radix. in the special case of base two or binary arithmetic, a number a has the floating point representation: n a = f * (2 e ) , f = ? { a(k) * (2 -k ) } k=1 where f is the fraction or mantissa, e is the exponent or characteristic, n is the number of bits in f and a(k), k=1,..,n are the bit values of f with a(1)=msb. typically, the mantissa is in normalized sign-magnitude represen- tation with implicit msb equal to one, and e is stored in biased form, where the bias is the magnitude of the most negative possible exponent [1,2] . if m is the number of bits in the biased exponent e b : e b = e + 2 m-1 using biased exponents permits comparison of expo- nents through a simple unsigned comparator, and fur- ther results in a unique representation of zero given by f = eb = 0. algorithms for radix conversion are discussed in appendix a, and can be used to produce the binary floating point representation of a given decimal number. examples of sign-magnitude floating point representa- tions of some decimal numbers are as follows: decimal e f 1.0 1 .10000000 0.15625 -2 .10100000 0.1 -3 .110011001100.... 1.23x10 3 11 .10011001110 it is important to note that the only numbers that can be represented exactly in binary arithmetic are those which are sums of powers of two, resulting in non-terminating binary representations of some simple decimal numbers such as .1 as shown above, and leading to truncation errors regardless of the value of n. floating point calculations, even involving numbers admitting an exact binary representation, usually lose information after truncation to an n bit result, and therefore require some rounding scheme to minimize such roundoff errors [1] . author: frank testa www.datasheet.co.kr datasheet pdf - http://www..net/
ds00575a-page 2 ? 1994 microchip technology inc. ieee 754 compliant floating-point routines rounding methods truncation of a binary representation to n bits is severely biased since it always leads to a number whose magni- tude is less than or equal to that of the exact value, thereby possibly causing significant error buildup during a long sequence of calculations. simple adder-based rounding by adding the nsb to the lsb is unbiased except when the value to be rounded is equidistant from the two nearest n bit values [1] . in this case, magnitudes are always rounded up thereby producing a small but still undesirable bias. this can be removed by stipulating that in the equidistant case, the n bit value with lsb=0 is selected, commonly referred to as the rounding to the nearest method, the default mode in the ieee754 stan- dard [4,5] . the number of guard bits or extra bits of precision, is related to the sensitivity of the rounding method since using more guard bits results in fewer equidistant cases to be resolved. since more than one guard bit requires an extra byte in pic16/17 arithmetic, only one guard bit, usually handled in the carry bit, is employed in this library of floating point routines. near- est neighbor rounding with one guard bit leads to the following simple result: n bit value guard bit result a 0 round to a a 1 if a,lsb=0, round to a if a,lsb=1, round to a+1 a+1 0 round to a+1 another interesting rounding method, is von neumann rounding or jamming, where the exact number is trun- cated to n bits and then set lsb=1. although the errors can be twice as large as in round to the nearest, it is unbiased and requires little more effort than trunca- tion [1] . floating point formats in what follows, we use the following floating point formats: eb radix f0 f1 f2 point ieee754 xxxxxxxx . sxxxxxxx xxxxxxxx xxxxxxxx 32-bit truncated xxxxxxxx . sxxxxxxx xxxxxxxx 24-bit where eb is the biased 8-bit exponent, with bias=2 7 =128= 0x80, s is the sign bit, and bytes f0, f1 and f2 constitute the mantissa with f0 the most significant byte with implicit msb = 1. it is important to note that the ieee754 standard format [4] places the sign bit as the msb of eb with the lsb of the exponent as the msb of f0. because of the inherent byte structure of the pic16/17 family of microcontrollers, more efficient code was possible by adopting the above formats rather than strictly adhering to the ieee standard. the limiting absolute values of the above floating point formats are given as follows: |a| 32-bit format eb e f decimal max 0xff7fffff ff 7f 7fffff 1.7014117e+38 min 0x01000000 01 81 000000 2.9387359e-39 where the msb is implicitly equal to one, and its bit location is occupied by the sign bit. the 24-bit format has the same structure but with only a 16-bit mantissa. while 24- to 32-bit conversion is trivial, requiring only an additional zero byte in the mantissa, a 32- to 24-bit conversion routine would typically employ nearest neigh- bor rounding before truncation. to produce the correct representation of a particular decimal number, a high-level language compiler and debugger could be used to display the internal binary representation on a host computer and make the appro- priate conversion to the above format. if this approach is not feasible, algorithms for producing this representa- tion are contained in appendix a. 5-12 www.datasheet.co.kr datasheet pdf - http://www..net/ ? 1994 microchip technology inc. ds00575a-page 3 ieee 754 compliant floating-point routines 5 floating point exceptions although the dynamic range of mathematical calcula- tions is increased through floating point arithmetic, over- flow and underflow are both possible when the limiting values of the representation are exceeded, such as in multiplication requiring the addition of exponents, or in division with the difference of exponents [2] . in these operations, mantissa calculations followed by appropri- ate normalizing and exponent modification can also lead to overflow or underflow in special cases. similarly, addition and subtraction after mantissa alignment, fol- lowed by normalization can also lead to such excep- tions. furthermore, if nearest neighbor rounding is en- abled, floating point overflow can occur in the case of rounding 0xff7fffff with nsb=1 since adding the nsb would be required, resulting in mantissa overflow followed by a right shift and increment of the exponent, thus producing exponent overflow. data ram requirements the following contiguous data ram locations are used by the library: exp = aexp aarg and acc exponent acc+b0 = aarg+b0 aarg and acc mantissa acc+b1 = aarg+b1 acc+b2 = aarg+b2 acc+b3 additional acc storage acc+b4 acc+b5 sign sign in msb fpflags exception flags, option bits bexp barg exponent barg+b0 barg mantissa barg+b1 barg+b2 temp+b0 temporary storage temp+b1 where bx = x. 5-13 the exception flags and option bits in fpflags are defined as follows: sat rnd fdz fun fov iov fpflags 76543210 iov integer overflow flag fov floating point overflow flag fun floating point underflow flag fdz floating point divide by zero flag rnd nearest neighbor rounding enable bit sat saturate enable bit usage for the unary operations, input argument and result are in aarg. the binary operations require input argu- ments in aarg and barg, and produces the result in aarg, thereby simplifying sequencing of operations. exception handling all routines return wreg = 0x00 upon successful comple- tion and wreg = 0xff, together with the appropriate flag bit set upon exception. if sat = 0, saturation is disabled and spurious results are obtained in aarg upon an exception. if sat = 1, saturation is enabled and only overflow or underflow exceptions produce satu- rated results in aarg. saturation is not applied on a divide by zero exception. rounding with rnd = 0, rounding is disabled, and simple trunca- tion is used, resulting in some speed enhancement. if rnd = 1, nearest neighbor rounding is implemented. integer to float conversion the routine floxx converts the twos complement inte- ger in aarg to the above floating point representation, producing the result in aexp, aarg. the routine initial- izes the exponent to move the radix point to the left of the msb and then calls the normalize routine. an example is given by: flo24( 12106 ) = flo24( 0x2f4a ) = 0x8e3d28 = 12106.0 www.datasheet.co.kr datasheet pdf - http://www..net/ ds00575a-page 4 ? 1994 microchip technology inc. ieee 754 compliant floating-point routines normalize the routine nrmxx takes an unnormalized floating point number with all bits explicit in aexp, aarg and left shifts the mantissa and adjusts the exponent until the result has an explicit msb = 1, followed by application of the sign bit thereby making the msb implicit. this routine is called by floxx, fpaxx and fpsxx, and is usually not needed explicitly by the user since all operations pro- ducing a floating point result are implicitly normalized. float to integer conversion the routine intxx converts the normalized floating point number in aexp, aarg, to a twos complement integer in aarg. after removing the bias from aexp and precluding a result of zero or integer overflow, the mantissa in aarg is left shifted by aexp and converted to twos complement representation. as an example, consider: int24( 123.45 ) = int24( 0x87f6e6 ) = 0x7b = 123 addition/subtraction the floating point add routine fpaxx, takes the argu- ments in aexp, aarg and bexp, barg and returns the sum in aexp, aarg. if necessary, the arguments are swapped to insure that aexp >= bexp, and then barg is then aligned by right shifting by aexp - bexp. the mantissas are then added and the result is normal- ized by calling nrmxx. the subtract routine fpsxx simply toggles the sign bit in barg and calls fpaxx. several examples are as follows: fpa24( -.32212e+5,.11120e+4 ) = fpa24( 0x8ffba8, 0x8b0b00 ) = 0x8ff2f8 = -.31100e+5 fps24( .89010e+4,-.17802e+5 ) = fps24( 0x8e0b14, 0x8f8b14 ) = 0x8f509e = .26703e+5 multiplication the floating point multiply routine fpmxx, takes the arguments in aexp, aarg and bexp, barg and returns the product in aexp, aarg. after testing for a zero argument, the sign and exponent of the result are computed together with testing for overflow. the mantis- sas are then multiplied using a standard add-shift method, followed by postnormalization if necessary. for ex- ample, consider: fpm24( -.32212e+5,.11120e+4 ) = fpm24( 0x8ffba8, 0x8b0b00 ) = 0x9a88a4 = -.35820e+8 division the floating point divide routine fpdxx, takes the nu- merator in aexp, aarg and denominator in bexp, barg and returns the quotient in aexp, aarg. after testing for a zero denominator, the sign and exponent of the result are computed together with testing for divi- dend alignment. if the argument mantissas satisfy the inequality aarg >= barg, the dividend aarg is right shifted by one bit and the exponent is adjusted, thereby resulting in aarg < barg and the dividend is aligned. alignment permits a valid division sequence and elimi- nates the need for postnormalization. after testing for overflow or underflow as appropriate, the mantissas are then divided using a standard shift-subtract restoring method. a simple example is given by: fpd24( -.16106e+5, .24715e+5 ) = fpd24( 0x8efba8, 0x8f4116 ) = 0x80a6d4 = -.65167e+0 5-14 www.datasheet.co.kr datasheet pdf - http://www..net/ ? 1994 microchip technology inc. ds00575a-page 5 ieee 754 compliant floating-point routines 5 appendix a several algorithms for decimal to binary conversion are given below. the integer and fractional conversion algo- rithms are useful in both native assembly as well as high level languages, and comprise the basis for the floating point decimal to binary conversion algorithm a.3. algo- rithm a.4 is a more brute force method easily imple- mented on a calculator or in a high-level language on a host computer. a.1 integer conversion algorithm[3]: given an integer n, where d(k) are the bit values of its n bit binary representation with d(0)=lsb, n-1 n = ? { d(k) * (2 k ) } k=0 k=0 n(k) = n while n(k) =! 0 d(k) = remainder of n(k)/2 n(k+1) = [ n(k)/2 ] k = k + 1 endw where [ ] denotes the greatest integer function. a.2 fractional conversion algorithm[3]: given a fraction n, where d(k) are the bit values of its n bit binary representation with d(1)=msb: n n = ? { d(k) * (2 -k ) } k=1 k=0 n(k) = n while k <= n d(k) = [ n(k)*2 ] n(k+1) = fractional part of n(k)*2 k = k + 1 endw 5-15 a.3 floating point decimal to binary conversion algorithm[3]: given a decimal number a = f * 10 e , and the number of mantissa bits n, where f is not necessarily normalized, the binary floating point representation a = f * 2 e can be found as follows: normalize f and adjust e convert 10 e to the normalized binary representation f *2 e convert the fraction f to the binary fraction f using a.2 compute f = f * f normalize f and adjust e if necessary the conversion of the integer 10 e can be done with algorithm a.1, or if space is available, can be performed by a table lookup. furthermore, the conversion should be made using a number of guard bits and then rounded to an n bit result by the desired rounding method. a.4 floating point decimal to binary conversion algorithm: given a decimal number a, and the number of mantissa bits n, the bits in the mantissa of the above binary representation of a, a(k), k = 1,2,...,n, where a(1) = msb, are given by the following algorithm: z = ln a / ln 2 e = int ( z ) if e <= z e = e + 1 endif x = a / (2**e) k = 1 while k <= n if x >= 2**(-k) a(k) = 1 else a(k) = 0 endif x = x - a(k) * 2**(-k) k = k + 1 endw formally, the number a then has the floating point representation: n a = f * (2 e ) , f = ? { a(k) * (2 -k ) } k=1 www.datasheet.co.kr datasheet pdf - http://www..net/ ds00575a-page 6 ? 1994 microchip technology inc. ieee 754 compliant floating-point routines a simple fortran implementation of algorithm a.4 is given as follows: program fprep c implicit none c real*8 x,y,z c integer*4 k,n,p,a(32),eb,f,bias c parameter (bias=128) c 1 print 200 200 format(1x,enter n: ,$) read 100,n 100 format(i5) c 2 print 201 201 format(1x,enter y: ,$) read 101,y 101 format(e32.15) if(y.le.0.)goto 1 c f=0 z=dlog(y)/dlog(2.d0) p=int(z) if(dble(p).le.z)p=p+1 eb=p+bias x=y*2.**(-p) do k=1,n if(x.ge.2.**(-k))then a(k)=1 else a(k)=0 endif if(a(k).ne.0)f=ibset(f,31-k+1) x=x-dble(a(k))*2.**(-k) enddo c print 300,p,(a(k),k=1,n) 300 format(1x,i5,3x,8(i2,i2,i2,i2,1x)) c print 400,eb,f 400 format(1x,z4,2x,z8) c goto 2 c end glossary biased exponents - nonnegative representation of exponents produced by adding the absolute value of the most negative exponent to a twos complement expo- nent. floating point underflow - occurs when the real number to be represented is smaller in absolute value than the smallest floating point number. floating point overflow - occurs when the real number to be represented is larger in absolute value than the largest floating point number. guard bits - additional bits of precision carried in a calculation for improved rounding sensitivity. lsb - least significant bit msb - most significant bit nearest neighbor rounding - an unbiased rounding method where a number to be rounded is rounded to its nearest neighbor in the representation, with the stipulation that if equidistant from its nearest neighbors, the neighbor with lsb equal to zero is selected. normalization - the process of left shifting the mantissa of an unnormalized floating point number until the msb equals one, while decreasing the exponent by the number of left shifts. nsb - next significant bit just to the right of the lsb. ones complement - a special case of the dimin- ished radix complement for radix two systems where the value of each bit is reversed. although sometimes used in representing positive and negative numbers, it pro- duces two representations of the number zero. radix - the base of a given number system. radix point - separates the integer and fractional parts of a number. saturation - mode of operation where integer and floating point numbers are fixed at there limiting values when an underflow or overflow is detected. sign magnitude - representation of positive and negative binary numbers where the absolute value is expressed together with the appropriate value of the sign bit. truncation - discarding any bits to the right of a given bit location. twos complement - a special case of radix comple- ment for radix two systems where the value of each bit is reversed and the result is incremented by one. pro- ducing a unique representation of zero, and covering the range -2**(n-1) to 2**(n-1)-1, this is more easily applied in addition and subtraction operations and is therefore the most commonly used method of representing posi- tive and negative numbers. 5-16 www.datasheet.co.kr datasheet pdf - http://www..net/ ? 1994 microchip technology inc. ds00575a-page 7 ieee 754 compliant floating-point routines 5 figure 1: integer to float conversion 5-17 flo24 yes no a < 0 nrm24 expdec = 0 ahi = 0 ahi nibble res024 ahi ms8 exp < expdec setfun24 exp = exp - expdec set fun flag sat = 0 axsign24 restore sign msb to a msb return ff return ff return 0 res024 return 0 a = 0 initialize exp add bias clear sign a = -a set sign msb ahi = alo alo = 0 expdec = 8 alo = 0 = 0 = 0 left shift a by 1-bit expdec = expdec + 1 saturate to smallest number module sign bit shift a by nibble expdec = expdec + 4 yes no no no yes yes no yes yes no no yes www.datasheet.co.kr datasheet pdf - http://www..net/ ds00575a-page 8 ? 1994 microchip technology inc. ieee 754 compliant floating-point routines figure 2: float to integer conversion 5-18 int24 yes no exp < 0 exp = 0 sign bit = 0 setiov24 a = -a set iov flag sat = 0 return 0 return ff save sign make msb explicit exp = exp - bias exp = 0 add next significant bit for rounding saturate to largest two's complement integer right shift by 1-bit exp = exp - 1 yes no yes no no yes no res024 exp > 16 exp < 8 yes no right shift by byte exp = exp - 8 setiov24 exp > 4 yes right shift by nibble exp = exp - 4 exp = 0 rnd = 0 msb = 1 yes yes yes no no no yes no no www.datasheet.co.kr datasheet pdf - http://www..net/ ? 1994 microchip technology inc. ds00575a-page 9 ieee 754 compliant floating-point routines 5 figure 3: floating point multiply fpm24 yes no a = 0 or b = 0 compute sign exp = aexp - bias + bexp yes res024 carry = 1 add - shift multiply carry = 1 no yes no rnd = 0 add next significant bit for rounding carry = 1 right shift by 1-bit exp = exp + 1 carry = 1 setfov24 overwrite explicit msb with sign bit return 0 no no yes yes no yes setfov24 make msb's explicit normalize by 1-bit exp = exp - 1 set fov flag sat = 0 no yes saturate to largest number modulo sign bit return ff 5-19 www.datasheet.co.kr datasheet pdf - http://www..net/ ds00575a-page 10 ? 1994 microchip technology inc. ieee 754 compliant floating-point routines figure 4: floating point divide 5-20 fdp24 yes no b = 0 compute sign make msb's explicit yes return ff a > b mantissas no compute exp aexp > bexp no yes shift-restore division set fdz flag align dividend no underflow? overflow? setfov24 yes setfun24 yes rnd = 0 compute next significant bit and add for rounding carry = 1 right shift by 1-bit exp = exp + 1 carry = 1 setfov24 overwrite explicit msb with sign bit return 0 no no yes yes no yes www.datasheet.co.kr datasheet pdf - http://www..net/ ? 1994 microchip technology inc. ds00575a-page 11 ieee 754 compliant floating-point routines 5 figure 5: floating point subtract 5-21 fps24 save xor of signs in temp aexp < bexp save sign of a in sign make msb's explicit no yes swap a and b no bexp > 8 return 0 rnd = 0 carry = 1 right shift by 1-bit exp = exp + 1 carry = 1 setfov24 toggle b sign bit fpa24 compute shift count in bexp bexp > 4 bexp > 8 bexp = 0 right shift b by byte bexp = bexp - 8 right shift b by nibble bexp = bexp - 4 restore sign in a yes yes no no yes yes right shift b by 1-bit bexp = bexp - 1 bexp = 0 yes no no add next significant bit for rounding aligned24 no no yes yes no yes www.datasheet.co.kr datasheet pdf - http://www..net/ ds00575a-page 12 ? 1994 microchip technology inc. ieee 754 compliant floating-point routines figure 6: normalization references 1. cavanagh, j.j.f., digital computer arithmetic, mcgraw-hill,1984. 2. hwang, k., computer arithmetic, john wiley & sons, 1979. 3. scott, n.r., computer number systems & arith- metic, prentice hall, 1985. 4. ieee standards board, ieee standard for floating- point arithmetic, ansi/ieee std 754-1985, ieee, 1985. 5. knuth, d.e., the art of computer programming, volume 2, addison-wesley, 1981. 5-22 aligned24 no yes b = - b no yes temp msb a = a + b carry = 1 carry = 1 right shift 1-bit exp = exp + 1 exp = 0 overwrite explicit msb with sign bit setfov24 return 0 nrm24 a = -a toggle sign bit nrm24 = 0 temp msb = 0 yes yes no yes no no www.datasheet.co.kr datasheet pdf - http://www..net/ ? 1994 microchip technology inc. ds00575a-page 13 ieee 754 compliant floating-point routines 5 routine max cycles min. cycles pm dm flo24 48 / 54 21 / 26 72 6 int24 57 / 65 11 / 28 101 6 nrm24 39 / 46 15 / 20 63 6 fpa24 116 / 131 31 212 10 fps24 117 / 132 32 213 10 fpm24 175 / 189 10 / 70 224 10 fpd24 328 / 352 11 / 277 377 11 1262 11 total memory flo32 60 / 67 26 / 30 120 7 int32 69 / 76 12 / 30 155 7 nrm32 48 / 55 20 / 24 108 7 fpa32 144 / 159 34 329 12 fps32 145 / 160 35 330 12 fpm32 320 / 336 11 / 88 382 13 fpd32 597 / 627 12 / 478 661 14 2085 14 total memory table 1: pic17cxx floating point performance data routine max cycles min. cycles pm dm flo24 83 / 88 21 / 25 37 6 int24 80 / 89 14 / 31 64 6 nrm24 72 / 77 14 / 18 26 6 fpa24 194 / 210 44 102 11 fps24 196 / 212 46 104 11 fpm24 298 / 313 11 / 218 80 11 fpd24 469 / 495 348 117 11 530 11 total memory flo32 104 / 110 24 / 34 52 7 int32 90 / 100 15 / 32 83 6 nrm32 90 / 96 18 / 28 38 7 fpa32 248 / 268 50 136 14 fps32 250 / 270 52 138 14 fpm32 574 / 591 12 / 315 94 14 fpd32 929 / 968 704 152 14 693 14 total memory table 2: pic16c5x / pic16cxx floating point performance data 5-23 www.datasheet.co.kr datasheet pdf - http://www..net/ ds00575a-page 14 ? 1994 microchip technology inc. ieee 754 compliant floating-point routines appendix a ; pic16 24 bit floating point library version 1.14 ; unary operations: both input and output are in aexp,aarg ; binary operations: input in aexp,aarg and bexp,barg with output in aexp,aarg ; all routines return wreg = 0x00 for successful completion, and wreg = 0xff ; for an error condition specified in fpflags. ; all timings are worst case cycle counts ; ; routine function ; ; flo24 16 bit integer to 24 bit floating point conversion ; ; timing: rnd ; 0 1 ; ; 0 83 83 ; sat ; 1 88 88 ; nrm24 normalization of unnormalized 24 bit floating point numbers ; timing: rnd ; 0 1 ; 0 72 72 ; sat ; 1 77 77 ; int24 24 bit floating point to 16 bit integer conversion ; timing: rnd ; 0 1 ; 0 80 86 ; sat ; 1 80 89 ; fpa24 24 bit floating point add ; timing: rnd ; 0 1 ; 0 194 205 ; sat ; 1 194 210 ; fps24 24 bit floating point subtract ; timing: rnd ; 0 1 ; 0 196 207 ; sat ; 1 196 212 ; fpm24 24 bit floating point multiply ; timing: rnd 5-24 www.datasheet.co.kr datasheet pdf - http://www..net/ ? 1994 microchip technology inc. ds00575a-page 15 ieee 754 compliant floating-point routines 5 ; 0 1 ; 0 298 309 ; sat ; 1 298 313 ; fpd24 24 bit floating point divide ; timing: rnd ; 0 1 ; 0 469 491 ; sat ; 1 469 495 list r=dec,x=on,t=off,p=16c71 include ds00575a-page 16 ? 1994 microchip technology inc. ieee 754 compliant floating-point routines ; define floating point library exception flags fpflags equ 0x14 ; floating point library exception flags iov equ 0 ; bit0 = integer overflow flag fov equ 1 ; bit1 = floating point overflow flag fun equ 2 ; bit2 = floating point underflow flag fdz equ 3 ; bit3 = floating point divide by zero flag rnd equ 6 ; bit6 = floating point rounding flag, 0 = truncation ; 1 = rounding to nearest lsb sat equ 7 ; bit7 = floating point saturate flag, 0 = terminate on ; exception without saturation, 1 = terminate on ; exception with saturation to appropriate value ;********************************************************************************************** ;********************************************************************************************** ; integer to float conversion ; input: 16 bit 2s complement integer right justified in aarg+b0, aarg+b1 ; use: call flo24 ; output: 24 bit floating point number in aexp, aarg+b0, aarg+b1 ; result: aarg < float( aarg ) ; max timing: 11+72 = 83 clks sat = 0 ; 11+77 = 88 clks sat = 1 ; min timing: 7+14 = 21 clks aarg = 0 ; 7+18 = 25 clks ; pm: 11+26 = 37 dm: 6 flo24 movlw 16+expbias ; initialize exponent and add bias movwf exp movf acc+b0,w movwf sign btfss acc+b0,msb ; test sign goto nrm24 comf acc+b1 ; if < 0, negate and set msb in sign comf acc+b0 incf acc+b1 btfsc _z incf acc+b0 ; ; normalization routine ; input: 24 bit unnormalized floating point number in aexp, aarg+b0, aarg+b1, ; with sign in sign,msb and other bits zero. ; use: call nrm24 ; output: 24 bit normalized floating point number in aexp, aarg+b0, aarg+b1 ; result: aarg < normalize( aarg ) ; max timing: 10+6+7*7+7 = 72 clks sat = 0 ; 10+6+7*7+1+11 = 77 clks sat = 1 ; min timing: 14 clks aarg = 0 5-26 www.datasheet.co.kr datasheet pdf - http://www..net/ ? 1994 microchip technology inc. ds00575a-page 17 ieee 754 compliant floating-point routines 5 ; 5+9+4 = 18 clks ; pm: 26 dm: 6 nrm24 clrf temp ; clear exponent decrement movf acc+b0,w ; test if highbyte=0 btfss _z goto norm24 movf acc+b1,w ; if so, shift 8 bits by move movwf acc+b0 btfsc _z ; if highbyte=0, result=0 goto res024 clrf acc+b1 bsf temp,3 norm24 movf temp,w subwf exp btfss _z btfss _c goto setfun24 bcf _c ; clear carry bit norm24a btfsc acc+b0,msb ; if msb=1, normalization done goto fixsign24 rlf acc+b1 ; otherwise, shift left and rlf acc+b0 ; decrement exp decfsz exp goto norm24a goto setfun24 ; underflow if exp=0 fixsign24 btfss sign,msb bcf acc+b0,msb ; clear explicit msb if positive retlw 0 ;********************************************************************************************** ;********************************************************************************************** ; float to integer conversion ; input: 24 bit floating point number in aexp, aarg+b0, aarg+b1 ; use: call int24 ; output: 16 bit 2s complement integer right justified in aarg+b0, aarg+b1 ; result: aarg < int( aarg ) ; max timing: 26+6*6+5+13 = 80 clks rnd = 0 ; 26+6*6+5+19 = 86 clks rnd = 1, sat = 0 ; 26+6*6+5+22 = 89 clks rnd = 1, sat = 1 ; min timing: 9+5 = 14 clks aarg = 0 ; 19+5+7 = 31 clks ; pm: 64 dm: 6 int24 movf acc+b0,w ; save sign in sign movwf sign bsf acc+b0,msb ; make msb explicit movlw expbias ; remove bias from exp subwf exp btfss exp,msb ; if <= 0, result=0 btfsc _z goto res024 movf exp,w 5-27 www.datasheet.co.kr datasheet pdf - http://www..net/ ds00575a-page 18 ? 1994 microchip technology inc. ieee 754 compliant floating-point routines sublw 16 movwf exp btfss _z btfsc exp,msb goto setiov24 movlw 8 ; do byte shift if exp >= 8 subwf exp,w btfss _c goto shift24 movwf exp rlf acc+b1 ; rotate next bit for rounding movf acc+b0,w movwf acc+b1 clrf acc+b0 movf exp,w ; shift completed if exp = 0 btfsc _z goto shift24ok shift24 bcf _c rrf acc+b0 ; right shift by exp rrf acc+b1 decfsz exp goto shift24 shift24ok btfsc fpflags,rnd btfss acc+b1,lsb goto int24ok clrf acc+b2 rlf acc+b2,w addwf acc+b1 btfsc _z incf acc+b0 btfsc acc+b0,msb ; test for overflow goto setiov24 int24ok btfss sign,msb ; if sign bit set, negate retlw 0 comf acc+b1 comf acc+b0 incf acc+b1 btfsc _z incf acc+b0 retlw 0 res024 clrf acc+b0 ; integer result equals zero clrf acc+b1 clrf exp ; clear exp for other routines retlw 0 setiov24 bsf fpflags,iov ; set integer overflow flag btfss fpflags,sat ; test for saturation retlw 0xff ; return error code in wreg clrf acc+b0 ; saturate to largest twos btfss sign,msb ; complement 16 bit integer movlw 0xff movwf acc+b0 ; sign = 0, 0x 7f ff movwf acc+b1 ; sign = 1, 0x 80 00 rlf sign rrf acc+b0 retlw 0xff ; return error code in wreg ;********************************************************************************************** ;********************************************************************************************** ; floating point multiply 5-28 www.datasheet.co.kr datasheet pdf - http://www..net/ ? 1994 microchip technology inc. ds00575a-page 19 ieee 754 compliant floating-point routines 5 ; input: 24 bit floating point number in aexp, aarg+b0, aarg+b1 ; 24 bit floating point number in bexp, barg+b0, barg+b1 ; use: call fpm24 ; output: 24 bit floating point product in aexp, aarg+b0, aarg+b1 ; result: aarg < aarg * barg ; max timing: 25+15*16+15+18 = 298 clks rnd = 0 ; 25+15*16+15+29 = 309 clks rnd = 1, sat = 0 ; 25+15*16+15+33 = 313 clks rnd = 1, sat = 1 ; min timing: 6+5 = 11 clks aarg * barg = 0 ; 24+15*11+14+15 = 218 clks ; pm: 80 dm: 11 fpm24 movf aexp,w ; test for zero arguments btfss _z movf bexp,w btfsc _z goto res024 m24bne0 movf aarg+b0,w xorwf barg+b0,w movwf sign ; save sign in sign movf bexp,w addwf exp movlw expbias btfss _c goto mtun24 addwf exp btfsc _c goto setfov24 ; set multiply overflow flag goto mok24 mtun24 addwf exp btfss _c goto setfun24 mok24 bsf aarg+b0,msb ; make argument msbs explicit bsf barg+b0,msb bcf _c clrf acc+b2 ; clear initial partial product clrf acc+b3 movlw 16 movwf temp ; initialize counter mloop24 btfss aarg+b1,lsb ; test high byte goto mnoadd24 madd24 movf barg+b1,w addwf acc+b3 movf barg+b0,w btfsc _c incfsz barg+b0,w addwf acc+b2 mnoadd24 rrf acc+b2 rrf acc+b3 rrf acc+b0 rrf acc+b1 bcf _c decfsz temp goto mloop24 5-29 www.datasheet.co.kr datasheet pdf - http://www..net/ ds00575a-page 20 ? 1994 microchip technology inc. ieee 754 compliant floating-point routines btfsc acc+b2,msb ; check for postnormalization goto mround24 rlf acc+b0 rlf acc+b3 rlf acc+b2 decf exp mround24 btfsc fpflags,rnd btfss acc+b3,lsb goto mul24ok rlf acc+b0 ; rotate next significant bit into btfsc _c incf acc+b3 ; carry for rounding btfsc _z incf acc+b2 btfss _z ; has rounding caused carryout? goto mul24ok rrf acc+b2 ; if so, right shift rrf acc+b3 incf exp btfsc _c ; check for overflow goto setfov24 mul24ok btfss sign,msb bcf acc+b2,msb ; clear explicit msb if positive movf acc+b2,w movwf aarg+b0 ; move result to aarg movf acc+b3,w movwf aarg+b1 retlw 0 setfov24 bsf fpflags,fov ; set floating point underflag btfss fpflags,sat ; test for saturation retlw 0xff ; return error code in wreg movlw 0xff movwf aexp ; saturate to largest floating movwf aarg+b0 ; point number = 0x ff 7f ff movwf aarg+b1 ; modulo the appropriate sign bit rlf sign rrf aarg+b0 retlw 0xff ; return error code in wreg ;********************************************************************************************** ;********************************************************************************************** ; floating point divide ; input: 24 bit floating point dividend in aexp, aarg+b0, aarg+b1 ; 24 bit floating point divisor in bexp, barg+b0, barg+b1 ; use: call fpd24 ; output: 24 bit floating point quotient in aexp, aarg+b0, aarg+b1 ; result: aarg < aarg / barg ; max timing: 29+13+15*26+25+12 = 469 clks rnd = 0 ; 29+13+15*26+25+34 = 491 clks rnd = 1, sat = 0 ; 29+13+15*26+25+38 = 495 clks rnd = 1, sat = 1 ; min timing: 24+12+15*20+12 = 348 clks ; pm: 117 dm: 11 fpd24 movf bexp,w ; test for divide by zero 5-30 www.datasheet.co.kr datasheet pdf - http://www..net/ ? 1994 microchip technology inc. ds00575a-page 21 ieee 754 compliant floating-point routines 5 btfsc _z goto setfdz24 d24bne0 movf aarg+b0,w xorwf barg+b0,w movwf sign ; save sign in sign bsf aarg+b0,msb ; make argument msbs explicit bsf barg+b0,msb talign24 clrf temp ; clear align increment movf aarg+b0,w movwf acc+b2 ; test for alignment movf aarg+b1,w movwf acc+b3 movf barg+b1,w subwf acc+b3 movf barg+b0,w btfss _c incfsz barg+b0,w subwf acc+b2 clrf acc+b2 clrf acc+b3 btfss _c goto dalign24ok bcf _c ; align if necessary rrf acc+b0 rrf acc+b1 rrf acc+b2 movlw 0x01 movwf temp ; save align increment dalign24ok movf bexp,w ; compare aexp and bexp subwf exp btfss _c goto altb24 ageb24 movlw expbias addwf temp,w addwf exp btfsc _c goto setfov24 goto dargok24 ; set overflow flag altb24 movlw expbias addwf temp,w addwf exp btfss _c goto setfun24 ; set underflow flag dargok24 movlw 16 ; initialize counter movwf temp+b1 dloop24 rlf acc+b3 ; left shift rlf acc+b2 rlf acc+b1 rlf acc+b0 rlf temp movf barg+b1,w ; subtract subwf acc+b1 movf barg+b0,w btfss _c incfsz barg+b0,w subwf acc+b0 5-31 www.datasheet.co.kr datasheet pdf - http://www..net/ ds00575a-page 22 ? 1994 microchip technology inc. ieee 754 compliant floating-point routines rlf barg+b0,w iorwf temp btfss temp,lsb ; test for restore goto drest24 bsf acc+b3,lsb goto dok24 drest24 movf barg+b1,w ; restore if necessary addwf acc+b1 movf barg+b0,w btfsc _c incf barg+b0,w addwf acc+b0 bcf acc+b3,lsb dok24 decfsz temp+b1 goto dloop24 dround24 btfsc fpflags,rnd btfss acc+b3,lsb goto div24ok bcf _c rlf acc+b1 ; compute next significant bit rlf acc+b0 ; for rounding rlf temp movf barg+b1,w ; subtract subwf acc+b1 movf barg+b0,w btfss _c incfsz barg+b0,w subwf acc+b0 rlf barg+b0,w iorwf temp,w andlw 0x01 addwf acc+b3 btfsc _c incf acc+b2 btfss _z ; test if rounding caused carryout goto div24ok rrf acc+b2 rrf acc+b3 incf exp btfsc _z ; test for overflow goto setfov24 div24ok btfss sign,msb bcf acc+b2,msb ; clear explicit msb if positive movf acc+b2,w movwf aarg+b0 ; move result to aarg movf acc+b3,w movwf aarg+b1 retlw 0 setfun24 bsf fpflags,fun ; set floating point underflag btfss fpflags,sat ; test for saturation retlw 0xff ; return error code in wreg movlw 0x01 ; saturate to smallest floating movwf aexp ; point number = 0x 01 00 00 clrf aarg+b0 ; modulo the appropriate sign bit clrf aarg+b1 5-32 www.datasheet.co.kr datasheet pdf - http://www..net/ ? 1994 microchip technology inc. ds00575a-page 23 ieee 754 compliant floating-point routines 5 rlf sign rrf aarg+b0 retlw 0xff ; return error code in wreg setfdz24 bsf fpflags,fdz ; set divide by zero flag retlw 0xff ;********************************************************************************************** ;********************************************************************************************** ; floating point subtract ; input: 24 bit floating point number in aexp, aarg+b0, aarg+b1 ; 24 bit floating point number in bexp, barg+b0, barg+b1 ; use: call fps24 ; output: 24 bit floating point sum in aexp, aarg+b0, aarg+b1 ; result: aarg < aarg - barg ; max timing: 2+194 = 196 clks rnd = 0 ; 2+205 = 207 clks rnd = 1, sat = 0 ; 2+210 = 212 clks rnd = 1, sat = 1 ; min timing: 2+44 = 46 clks ; pm: 2+102 = 104 dm: 11 fps24 movlw 0x80 xorwf barg+b0 ; ; floating point add ; input: 24 bit floating point number in aexp, aarg+b0, aarg+b1 ; 24 bit floating point number in bexp, barg+b0, barg+b1 ; use: call fpa24 ; output: 24 bit floating point sum in aexp, aarg+b0, aarg+b1 ; result: aarg < aarg - barg ; max timing: 25+25+6*6+5+31+72 = 194 clks rnd = 0 ; 25+25+6*6+5+42+72 = 205 clks rnd = 1, sat = 0 ; 25+25+6*6+5+42+77 = 210 clks rnd = 1, sat = 1 ; min timing: 22+18+4 = 44 clks ; pm: 102 dm: 11 fpa24 movf aarg+b0,w ; exclusive or of signs in temp xorwf barg+b0,w movwf temp movf aexp,w ; use aarg if aexp >= bexp subwf bexp,w btfss _c goto usea24 movf bexp,w movwf acc+b2 ; otherwise, swap aarg and barg movf aexp,w movwf bexp movf acc+b2,w movwf aexp 5-33 www.datasheet.co.kr datasheet pdf - http://www..net/ ds00575a-page 24 ? 1994 microchip technology inc. ieee 754 compliant floating-point routines movf barg+b0,w movwf acc+b2 movf aarg+b0,w movwf barg+b0 movf acc+b2,w movwf aarg+b0 movf barg+b1,w movwf acc+b2 movf aarg+b1,w movwf barg+b1 movf acc+b2,w movwf aarg+b1 usea24 movf aarg+b0,w movwf sign ; save sign in sign bsf aarg+b0,msb ; make msbs explicit bsf barg+b0,msb movf barg+b0,w movwf acc+b2 movf barg+b1,w movwf acc+b3 movf bexp,w ; compute shift count in bexp subwf aexp,w movwf bexp btfsc _z goto around24 movlw 8 subwf bexp,w btfss _c ; if bexp >= 8, do byte shift goto alignb24 movwf bexp rlf acc+b3 ; rotate next bit for rounding movf acc+b2,w movwf acc+b3 clrf acc+b2 alignb24 movf bexp,w ; already aligned if bexp = 0 btfsc _z goto around24 aloopb24 bcf _c ; right shift by bexp rrf acc+b2 rrf acc+b3 decfsz bexp goto aloopb24 around24 btfsc fpflags,rnd btfss acc+b3,lsb goto aligned24 btfss _c goto aligned24 incf acc+b3 ; carry for rounding btfsc _z incf acc+b2 btfss _z goto aligned24 rrf acc+b2 rrf acc+b3 incf exp btfsc _z goto setfov24 aligned24 btfss temp,msb ; negate if signs opposite goto aok24 comf acc+b3 5-34 www.datasheet.co.kr datasheet pdf - http://www..net/ ? 1994 microchip technology inc. ds00575a-page 25 ieee 754 compliant floating-point routines 5 comf acc+b2 incf acc+b3 btfsc _z incf acc+b2 aok24 movf acc+b3,w ; add addwf aarg+b1 btfsc _c incf acc+b0 movf acc+b2,w addwf aarg+b0 btfsc temp,msb goto acomp24 btfss _c goto fixsign24 rrf aarg+b0 ; shift right and increment exp rrf aarg+b1 incfsz aexp goto fixsign24 goto setfov24 acomp24 btfsc _c goto nrm24 ; normalize and fix sign comf aarg+b1 ; negate, toggle sign bit and comf aarg+b0 ; then normalize incf aarg+b1 btfsc _z incf aarg+b0 movlw 0x80 xorwf sign goto nrm24 end 5-35 www.datasheet.co.kr datasheet pdf - http://www..net/ ds00575a-page 26 ? 1994 microchip technology inc. ieee 754 compliant floating-point routines appendix b ; pic17 24 bit floating point library version 1.14 ; unary operations: both input and output are in aexp,aarg ; binary operations: input in aexp,aarg and bexp,barg with output in aexp,aarg ; all routines return wreg = 0x00 for successful completion, and wreg = 0xff ; for an error condition specified in fpflags. ; max timings are worst case cycle counts, while min timings are non-exception ; best case cycle counts. ; routine function ; flo24 16 bit integer to 24 bit floating point conversion ; max timing: rnd ; 0 1 ; 0 48 48 ; sat ; 1 55 55 ; nrm24 normalization of unnormalized 24 bit floating point numbers ; max timing: rnd ; 0 1 ; 0 39 39 ; sat ; 1 46 46 ; int24 24 bit floating point to 16 bit integer conversion ; max timing: rnd ; 0 1 ; 0 57 61 ; sat ; 1 57 65 ; fpa24 24 bit floating point add ; max timing: rnd ; 0 1 ; 0 116 131 ; sat ; 1 116 131 ; fps24 24 bit floating point subtract ; max timing: rnd ; 0 1 ; 0 117 132 ; sat ; 1 117 132 ; fpm24 24 bit floating point multiply ; max timing: rnd ; 0 1 ; 0 175 184 5-36 www.datasheet.co.kr datasheet pdf - http://www..net/ ? 1994 microchip technology inc. ds00575a-page 27 ieee 754 compliant floating-point routines 5 ; sat ; 1 175 189 ; fpd24 24 bit floating point divide ; max timing: rnd ; 0 1 ; 0 328 347 ; sat ; 1 328 352 list r=dec,x=on,t=off,p=17c42 include ds00575a-page 28 ? 1994 microchip technology inc. ieee 754 compliant floating-point routines fpflags equ 0x20 ; floating point library exception flags iov equ 0 ; bit0 = integer overflow flag fov equ 1 ; bit1 = floating point overflow flag fun equ 2 ; bit2 = floating point underflow flag fdz equ 3 ; bit3 = floating point divide by zero flag rnd equ 6 ; bit6 = floating point rounding flag, 0 = truncation ; 1 = unbiased rounding to nearest lsb sat equ 7 ; bit7 = floating point saturate flag, 0 = terminate on ; exception without saturation, 1 = terminate on ; exception with saturation to appropriate value ;********************************************************************************************** ;********************************************************************************************** ; integer to float conversion ; input: 16 bit 2s complement integer right justified in aarg+b0, aarg+b1 ; use: call flo24 ; output: 24 bit floating point number in aexp, aarg+b0, aarg+b1 ; result: aarg < float( aarg ) ; max timing: 9+39 = 48 clks sat = 0 ; 9+45 = 54 clks sat = 1 ; min timing: 6+15 = 21 clks aarg = 0 ; 6+20 = 26 clks ; pm: 9+63 = 72 dm: 6 flo24 movlw 16+expbias ; initialize exponent and add bias movwf exp movfp acc+b0,sign ; save sign in sign btfss acc+b0,msb ; test sign goto nrm24 comf acc+b1 ; if < 0, negate, set msb in sign comf acc+b0 infsnz acc+b1 incf acc+b0 ; ; normalization routine ; input: 24 bit unnormalized floating point number in aexp, aarg+b0, aarg+b1, ; with sign in sign,msb. ; use: call nrm24 ; output: 24 bit normalized floating point number in aexp, aarg+b0, aarg+b1 ; result: aarg < normalize( aarg ) ; max timing: 3+12+16+8 = 39 clks sat = 0 ; 3+12+16+15 = 46 clks sat = 1 ; min timing: 10+5 = 15 clks aarg = 0 ; 3+5+4+8 = 20 clks ; pm: 63 dm: 6 5-38 www.datasheet.co.kr datasheet pdf - http://www..net/ ? 1994 microchip technology inc. ds00575a-page 29 ieee 754 compliant floating-point routines 5 nrm24 clrf temp,w ; clear exponent decrement cpfsgt acc+b0 ; test if highbyte=0 goto nrm24a tnib24 movlw 0xf0 ; test if highnibble=0 andwf acc+b0,w tstfsz wreg goto norm24 swapf acc+b0 ; if so, shift 4 bits swapf acc+b1,w andlw 0x0f addwf acc+b0 swapf acc+b1,w andlw 0xf0 movpf wreg,acc+b1 bsf temp,2 ; increase decrement by 4 norm24 bcf _c ; clear carry bit btfsc acc+b0,msb ; if msb=1, normalization done goto tnormun24 rlcf acc+b1 ; otherwise, shift left and rlcf acc+b0 ; increment decrement incf temp btfsc acc+b0,msb goto tnormun24 rlcf acc+b1 rlcf acc+b0 incf temp btfsc acc+b0,msb ; since highnibble != 0, at most goto tnormun24 ; 3 left shifts are required rlcf acc+b1 rlcf acc+b0 incf temp tnormun24 movfp temp,wreg ; if exp <= decrement in temp, cpfsgt exp ; floating point underflow has goto setfun24 ; occured subwf exp ; otherwise, compute exp fixsign24 btfss sign,msb bcf acc+b0,msb ; clear explicit msb if positive retlw 0 nrm24a movfp acc+b1,acc+b0 ; if so, shift 8 bits by move clrf acc+b1 bsf temp,3 ; increase decrement by 8 cpfsgt acc+b0 ; if highbyte=0, result=0 goto res024 movlw 0xf0 ; test if highnibble=0 andwf acc+b0,w tstfsz wreg goto norm24a swapf acc+b0 ; if so, shift 4 bits bsf temp,2 ; increase decrement by 4 norm24a bcf _c ; clear carry bit btfsc acc+b0,msb ; if msb=1, normalization done goto tnormun24 rlcf acc+b0 ; otherwise, shift left and incf temp ; increment decrement btfsc acc+b0,msb goto tnormun24 rlcf acc+b0 incf temp 5-39 www.datasheet.co.kr datasheet pdf - http://www..net/ ds00575a-page 30 ? 1994 microchip technology inc. ieee 754 compliant floating-point routines btfsc acc+b0,msb ; since highnibble != 0, at most goto tnormun24 ; 3 left shifts are required rlcf acc+b0 incf temp goto tnormun24 ;********************************************************************************************** ;********************************************************************************************** ; float to integer conversion ; input: 24 bit floating point number in aexp, aarg+b0, aarg+b1 ; use: call int24 ; output: 16 bit 2s complement integer right justified in aarg+b0, aarg+b1 ; result: aarg < int( aarg ) ; max timing: 11+34+12 = 57 clks rnd = 0 ; 11+34+16 = 61 clks rnd = 1, sat = 0 ; 11+34+20 = 65 clks rnd = 1, sat = 1 ; min timing: 6+5 = 11 clks aarg = 0 ; 11+10+7 = 28 clks ; pm: 101 dm: 6 int24 movfp acc+b0,sign ; save sign in sign bsf acc+b0,msb ; make msb explicit movlw expbias ; remove bias from exp cpfsgt exp ; if <= 0, result=0 goto res024 subwf exp movlw 16 cpfslt exp ; if >= 16, integer overflow goto setiov24 ; will occur subwf exp,w negw exp movlw 7 ; do byte shift if exp >= 8 cpfsgt exp goto snib24 subwf exp ; exp = exp - 7 rlcf acc+b1 ; rotate next bit for rounding movfp acc+b0,acc+b1 clrf acc+b0 dcfsnz exp ; exp = exp - 1 goto shift24ok ; shift completed if exp = 0 snib24a movlw 3 ; do nibble shift if exp >= 4 cpfsgt exp goto shift24a subwf exp ; exp = exp - 3 swapf acc+b1,w movfp wreg,acc+b2 ; save for rounding andlw 0x0f movpf wreg,acc+b1 rlcf acc+b2 ; rotate next bit for rounding dcfsnz exp ; exp = exp - 1 goto shift24ok ; shift completed if exp = 0 shift24a bcf _c ; at most 3 right shifts are required rrcf acc+b1 ; right shift by exp dcfsnz exp goto shift24ok ; shift completed if exp = 0 5-40 www.datasheet.co.kr datasheet pdf - http://www..net/ ? 1994 microchip technology inc. ds00575a-page 31 ieee 754 compliant floating-point routines 5 bcf _c rrcf acc+b1 dcfsnz exp goto shift24ok ; shift completed if exp = 0 bcf _c rrcf acc+b1 goto shift24ok snib24 movlw 3 ; do nibble shift if exp >= 4 cpfsgt exp goto shift24 subwf exp ; exp = exp - 3 swapf acc+b1,w movfp wreg,acc+b2 ; save for rounding andlw 0x0f movpf wreg,acc+b1 swapf acc+b0,w andlw 0xf0 addwf acc+b1 swapf acc+b0,w andlw 0x0f movpf wreg,acc+b0 rlcf acc+b2 ; rotate next bit for rounding dcfsnz exp ; exp = exp - 1 goto shift24ok ; shift completed if exp = 0 shift24 bcf _c ; at most 3 right shifts are required rrcf acc+b0 ; right shift by exp rrcf acc+b1 dcfsnz exp goto shift24ok ; shift completed if exp = 0 bcf _c rrcf acc+b0 rrcf acc+b1 dcfsnz exp goto shift24ok ; shift completed if exp = 0 bcf _c rrcf acc+b0 rrcf acc+b1 shift24ok btfsc fpflags,rnd btfss acc+b1,lsb goto int24ok clrf wreg addwfc acc+b1 ; add next bit for rounding addwfc acc+b0 btfsc acc+b0,msb goto setiov24 int24ok btfss sign,msb ; if sign bit set, negate retlw 0 comf acc+b1 comf acc+b0 infsnz acc+b1 incf acc+b0 retlw 0 res024 clrf acc+b0 ; integer result equals zero clrf acc+b1 clrf exp ; clear exp for other routines retlw 0 setiov24 bsf fpflags,iov ; set integer overflow flag btfss fpflags,sat ; test for saturation retlw 0xff ; return error code in wreg clrf acc+b0 ; saturate to largest twos btfss sign,msb ; complement 16 bit integer setf acc+b0 ; sign = 0, 0x 7f ff 5-41 www.datasheet.co.kr datasheet pdf - http://www..net/ ds00575a-page 32 ? 1994 microchip technology inc. ieee 754 compliant floating-point routines movpf acc+b0,acc+b1 ; sign = 1, 0x 80 00 rlcf sign rrcf acc+b0 retlw 0xff ; return error code in wreg ;********************************************************************************************** ;********************************************************************************************** ; floating point multiply ; input: 24 bit floating point number in aexp, aarg+b0, aarg+b1 ; 24 bit floating point number in bexp, barg+b0, barg+b1 ; use: call fpm24 ; output: 24 bit floating point product in aexp, aarg+b0, aarg+b1 ; result: aarg < aarg * barg ; max timing: 19+140+16 = 175 clks rnd = 0 ; 19+140+25 = 184 clks rnd = 1, sat = 0 ; 19+140+30 = 189 clks rnd = 1, sat = 1 ; min timing: 5+5 = 10 clks aarg * barg = 0 ; 13+5+37+15 = 70 clks ; pm: 21+169+34 = 224 dm: 10 mul16 macro ; max timing: 10+14*9+4 = 140 clks ; min timing: 33+4 = 37 clks ; pm: 3+16*2+4+14*9+4 = 169 dm: 6 variable i = 0 variable j = 1 bcf _c ; clear carry bit clrf acc+b2 ; clear initial partial product clrf acc+b3 while i < 16 if i < 8 btfsc aarg+b1,i ; test low byte else btfsc aarg+b0,i-8 ; test high byte endif goto madd24#v( i ) i += 1 endw ; we cannot get here since msbs are explicit madd240 movfp barg+b0,acc+b2 ; if we get here, acc=0 so move movfp barg+b1,acc+b3 ; barg for add rrcf acc+b2 rrcf acc+b3 5-42 www.datasheet.co.kr datasheet pdf - http://www..net/ ? 1994 microchip technology inc. ds00575a-page 33 ieee 754 compliant floating-point routines 5 while j < 15 if j < 8 btfss aarg+b1,j ; test low byte else btfss aarg+b0,j-8 ; test high byte endif goto mnoadd24#v( j ) madd24#v( j ) movfp barg+b1,wreg addwf acc+b3 ; add lsb movfp barg+b0,wreg addwfc acc+b2 ; add msb mnoadd24#v( j ) rrcf acc+b2 rrcf acc+b3 if j > 13 rrcf acc+b1 ; save bits for rounding endif if j < 14 bcf _c ; clear carry when rotate possible endif j += 1 endw madd2415 movfp barg+b1,wreg addwf acc+b3 ; add lsb movfp barg+b0,wreg addwfc acc+b2 ; add msb endm fpm24 clrf wreg ; test for zero arguments cpfseq bexp cpfsgt aexp goto res024 m24bne0 movfp aarg+b0,wreg xorwf barg+b0,w movpf wreg,sign ; save sign in sign movfp bexp,wreg addwf exp movlw expbias btfss _c goto mtun24 addwf exp ; remove bias and overflow test btfsc _c goto setfov24 goto mok24 mtun24 addwf exp ; remove bias and underflow test btfss _c 5-43 www.datasheet.co.kr datasheet pdf - http://www..net/ ds00575a-page 34 ? 1994 microchip technology inc. ieee 754 compliant floating-point routines goto setfun24 mok24 bsf aarg+b0,msb ; make argument msbs explicit bsf barg+b0,msb mul16 ; use macro for multiplication btfsc _c ; check for postnormalization goto mright24 decf exp goto mround24 mright24 rrcf acc+b2 rrcf acc+b3 rrcf acc+b1 mround24 btfsc fpflags,rnd btfss acc+b3,lsb goto mul24ok clrf wreg rlcf acc+b1 ; rotate next significant bit into addwfc acc+b3 ; carry for rounding addwfc acc+b2 btfss _c ; has rounding caused carryout? goto mul24ok rrcf acc+b2 ; if so, right shift rrcf acc+b3 infsnz exp ; test for floating point overflow goto setfov24 mul24ok btfss sign,msb bcf acc+b2,msb ; clear explicit msb if positive movfp acc+b2,aarg+b0 ; move result to aarg movfp acc+b3,aarg+b1 retlw 0 setfov24 bsf fpflags,fov ; set floating point underflag btfss fpflags,sat ; test for saturation retlw 0xff ; return error code in wreg setf aexp ; saturate to largest floating setf aarg+b0 ; point number = 0x ff 7f ff setf aarg+b1 ; modulo the appropriate sign bit rlcf sign rrcf aarg+b0 retlw 0xff ; return error code in wreg ;********************************************************************************************** ;********************************************************************************************** ; floating point divide ; input: 24 bit floating point dividend in aexp, aarg+b0, aarg+b1 ; 24 bit floating point divisor in bexp, barg+b0, barg+b1 ; use: call fpd24 ; output: 24 bit floating point quotient in aexp, aarg+b0, aarg+b1 ; result: aarg < aarg / barg ; max timing: 22+11+285+10 = 328 clks rnd = 0 ; 22+11+285+29 = 347 clks rnd = 1, sat = 0 ; 22+11+285+34 = 352 clks rnd = 1, sat = 1 ; min timing: 6+5 = 11 clks aarg = 0 ; 30+237+10 = 277 clks 5-44 www.datasheet.co.kr datasheet pdf - http://www..net/ ? 1994 microchip technology inc. ds00575a-page 35 ieee 754 compliant floating-point routines 5 ; pm: 36+301+40 = 377 dm: 11 div16 macro ; timing: 1+16*20 = 321 clks variable i = 0 bcf _c while i < 16 clrf temp ; left shift rlcf acc+b3 rlcf acc+b2 rlcf acc+b1 rlcf acc+b0 rlcf temp movfp barg+b1,wreg ; subtract subwf acc+b1 movfp barg+b0,wreg subwfb acc+b0 clrf wreg subwfb temp btfss _c ; test for restore goto drest#v( i ) bsf acc+b3,lsb goto dok#v( i ) drest#v( i ) movfp barg+b1,wreg ; restore if necessary addwf acc+b1 movfp barg+b0,wreg addwfc acc+b0 bcf acc+b3,lsb dok#v( i ) i += 1 endw endm div16a macro ; max timing: 15+15*18 = 285 clks ; min timing: 12+15*15 = 237 clks ; pm: 16+15*19 = 301 dm: 7 btg temp,lsb ; save carry movfp barg+b1,wreg ; subtract subwf acc+b1 movfp barg+b0,wreg subwfb acc+b0 rlcf wreg iorwf temp btfss temp,lsb ; test for restore goto darest0 bsf acc+b2,msb goto daok0 5-45 www.datasheet.co.kr datasheet pdf - http://www..net/ ds00575a-page 36 ? 1994 microchip technology inc. ieee 754 compliant floating-point routines darest0 movfp barg+b1,wreg ; restore if necessary addwf acc+b1 movfp barg+b0,wreg addwfc acc+b0 bcf acc+b2,msb daok0 variable i = 1 while i < 16 bcf _c rlcf acc+b1 rlcf acc+b0 rlcf temp ; save carry movfp barg+b1,wreg ; subtract subwf acc+b1 movfp barg+b0,wreg subwfb acc+b0 rlcf wreg iorwf temp btfss temp,lsb ; test for restore goto darest#v( i ) if i < 8 bsf acc+b2,msb-i ; set bit in quotient else bsf acc+b3,15-i ; set bit in quotient endif goto daok#v( i ) darest#v( i ) movfp barg+b1,wreg ; restore if necessary addwf acc+b1 movfp barg+b0,wreg addwfc acc+b0 if i < 8 bcf acc+b2,msb-i ; clear bit in quotient else bcf acc+b3,15-i ; clear bit in quotient endif daok#v( i ) i += 1 endw endm fpd24 clrf temp,w ; test for divide by zero cpfsgt bexp goto setfdz24 5-46 www.datasheet.co.kr datasheet pdf - http://www..net/ ? 1994 microchip technology inc. ds00575a-page 37 ieee 754 compliant floating-point routines 5 cpfsgt aexp goto res024 d24bne0 movfp aarg+b0,wreg xorwf barg+b0,w movpf wreg,sign ; save sign in sign bsf aarg+b0,msb ; make argument msbs explicit bsf barg+b0,msb talign24 incf temp ; set align increment movfp aarg+b0,acc+b2 ; test for alignment movfp aarg+b1,acc+b3 movfp barg+b1,wreg subwf acc+b3 movfp barg+b0,wreg subwfb acc+b2 btfsc _c goto dalign24ok rlcf acc+b1 ; align if necessary rlcf acc+b0 decf temp ; fix align increment dalign24ok movfp bexp,wreg ; compute aexp - bexp subwf exp movlw expbias btfss _c goto altb24 ageb24 addwf temp,w ; if aexp > bexp, test for addwf exp ; overflow btfsc _c goto setfov24 goto dargok24 altb24 addwf temp,w ; if aexp < bexp, test for addwf exp ; underflow btfss _c goto setfun24 dargok24 div16a ; macro for division dround24 btfsc fpflags,rnd btfss acc+b3,lsb goto div24ok bcf _c ; compute next significant bit rlcf acc+b1 ; for rounding rlcf acc+b0 rlcf temp ; save carry movfp barg+b1,wreg ; subtract subwf acc+b1 movfp barg+b0,wreg subwfb acc+b0 rlcf wreg iorwf temp rrcf temp ; rotate next significant bit into clrf wreg ; carry and add for rounding addwfc acc+b3 addwfc acc+b2 btfss _c ; test if rounding caused carryout goto div24ok rrcf acc+b2 rrcf acc+b3 infsnz exp ; test for overflow goto setfov24 5-47 www.datasheet.co.kr datasheet pdf - http://www..net/ ds00575a-page 38 ? 1994 microchip technology inc. ieee 754 compliant floating-point routines div24ok btfss sign,msb bcf acc+b2,msb ; clear explicit msb if positive movfp acc+b2,aarg+b0 ; move result to aarg movfp acc+b3,aarg+b1 retlw 0 setfun24 bsf fpflags,fun ; set floating point underflag btfss fpflags,sat ; test for saturation retlw 0xff ; return error code in wreg movlw 0x01 ; saturate to smallest floating movpf wreg,aexp ; point number = 0x 01 00 00 clrf aarg+b0 ; modulo the appropriate sign bit clrf aarg+b1 rlcf sign rrcf aarg+b0 retlw 0xff ; return error code in wreg setfdz24 bsf fpflags,fdz ; set floating point divide by zero retlw 0xff ; flag and return error code in ; wreg ;********************************************************************************************** ;********************************************************************************************** ; floating point subtract ; input: 24 bit floating point number in aexp, aarg+b0, aarg+b1 ; 24 bit floating point number in bexp, barg+b0, barg+b1 ; use: call fps24 ; output: 24 bit floating point difference in aexp, aarg+b0, aarg+b1 ; result: aarg < aarg - barg ; max timing: 1+116 = 117 clks rnd = 0 ; 1+131 = 132 clks rnd = 1 ; min timing: 1+31 = 32 clks ; pm: 1+212 = 213 dm: 10 fps24 btg barg+b0,msb ; toggle sign bit for subtraction ; ; floating point add ; input: 24 bit floating point number in aexp, aarg+b0, aarg+b1 ; 24 bit floating point number in bexp, barg+b0, barg+b1 ; use: call fpa24 ; output: 24 bit floating point sum in aexp, aarg+b0, aarg+b1 ; result: aarg < aarg - barg ; max timing: 60+17+39 = 116 clks rnd = 0 ; 60+25+46 = 131 clks rnd = 1 ; min timing: 27+4 = 31 clks ; pm: 212 dm: 10 fpa24 movfp aarg+b0,wreg ; exclusive or of signs in temp xorwf barg+b0,w movpf wreg,temp 5-48 www.datasheet.co.kr datasheet pdf - http://www..net/ ? 1994 microchip technology inc. ds00575a-page 39 ieee 754 compliant floating-point routines 5 movfp aexp,wreg ; use aarg if aexp >= bexp cpfsgt bexp goto usea24 useb24 movfp barg+b0,sign ; save sign in sign bsf barg+b0,msb ; make msbs explicit bsf aarg+b0,msb movfp aexp,wreg ; compute shift count in bexp movfp bexp,aexp subwf bexp btfsc _z goto bligned24 movlw 7 cpfsgt bexp ; do byte shift if bexp >= 8 goto bnib24 subwf bexp ; bexp = bexp - 7 rlcf aarg+b1 ; rotate next bit for rounding movfp aarg+b0,aarg+b1 clrf aarg+b0 dcfsnz bexp ; bexp = bexp - 1 goto bround24 cpfsgt bexp ; if bexp still >= 8, then goto bnib24a ; aarg = 0 relative to barg movfp sign,aarg+b0 ; return barg movfp barg+b1,aarg+b1 retlw 0x00 bnib24a movlw 3 ; do nibbleshift if bexp >= 4 cpfsgt bexp goto bloop24a subwf bexp ; bexp = bexp -3 swapf aarg+b1,w movpf wreg,acc+b4 ; save for rounding andlw 0x0f movpf wreg,aarg+b1 rlcf acc+b4 ; rotate next bit for rounding dcfsnz bexp ; bexp = bexp - 1 goto bround24 ; aligned if bexp = 0 bloop24a bcf _c ; right shift by bexp rrcf aarg+b1 dcfsnz bexp goto bround24 ; aligned if bexp = 0 bcf _c rrcf aarg+b1 dcfsnz bexp goto bround24 ; aligned if bexp = 0 bcf _c ; at most 3 right shifts are rrcf aarg+b1 ; possible goto bround24 bnib24 movlw 3 ; do nibbleshift if bexp >= 4 cpfsgt bexp goto bloop24 subwf bexp ; bexp = bexp -3 swapf aarg+b1,w movpf wreg,acc+b4 ; save for rounding andlw 0x0f movpf wreg,aarg+b1 swapf aarg+b0,w andlw 0xf0 addwf aarg+b1 swapf aarg+b0,w 5-49 www.datasheet.co.kr datasheet pdf - http://www..net/ ds00575a-page 40 ? 1994 microchip technology inc. ieee 754 compliant floating-point routines andlw 0x0f movpf wreg,aarg+b0 rlcf acc+b4 ; rotate next bit for rounding dcfsnz bexp ; bexp = bexp - 1 goto bround24 ; aligned if bexp = 0 bloop24 bcf _c ; right shift by bexp rrcf aarg+b0 rrcf aarg+b1 dcfsnz bexp goto bround24 ; aligned if bexp = 0 bcf _c rrcf aarg+b0 rrcf aarg+b1 dcfsnz bexp goto bround24 ; aligned if bexp = 0 bcf _c ; at most 3 right shifts are rrcf aarg+b0 ; possible rrcf aarg+b1 bround24 btfsc fpflags,rnd btfss aarg+b1,lsb goto bligned24 clrf wreg addwfc aarg+b1 ; add carry for rounding addwfc aarg+b0 btfss _c ; has rounding caused carryout? goto bligned24 rrcf aarg+b0 ; if so, right shift rrcf aarg+b1 infsnz exp ; test for floating point overflow goto setfov24 bligned24 btfss temp,msb ; negate if signs opposite goto aok24 comf aarg+b1 comf aarg+b0 infsnz aarg+b1 incf aarg+b0 goto aok24 usea24 movfp aarg+b0,sign ; save sign in sign bsf aarg+b0,msb ; make msbs explicit bsf barg+b0,msb movfp bexp,wreg ; compute shift count in bexp subwf aexp,w movpf wreg,bexp btfsc _z goto aligned24 movlw 7 cpfsgt bexp ; do byte shift if bexp >= 8 goto anib24 subwf bexp ; bexp = bexp - 7 rlcf barg+b1 ; rotate next bit for rounding movfp barg+b0,wreg movpf wreg,barg+b1 clrf barg+b0 dcfsnz bexp ; bexp = bexp - 1 goto around24 cpfsgt bexp ; if bexp still >= 8, then goto anib24a ; barg = 0 relative to aarg movfp sign,aarg+b0 ; return aarg 5-50 www.datasheet.co.kr datasheet pdf - http://www..net/ ? 1994 microchip technology inc. ds00575a-page 41 ieee 754 compliant floating-point routines 5 retlw 0x00 anib24a movlw 3 ; do nibbleshift if bexp >= 4 cpfsgt bexp goto aloop24a subwf bexp ; bexp = bexp -3 swapf barg+b1,w movpf wreg,acc+b4 ; save for rounding andlw 0x0f movpf wreg,barg+b1 rlcf acc+b4 ; rotate next bit for rounding dcfsnz bexp ; bexp = bexp - 1 goto around24 ; aligned if bexp = 0 aloop24a bcf _c ; right shift by bexp rrcf barg+b1 dcfsnz bexp goto around24 ; aligned if bexp = 0 bcf _c rrcf barg+b1 dcfsnz bexp goto around24 ; aligned if bexp = 0 bcf _c ; at most 3 right shifts are rrcf barg+b1 ; possible goto around24 anib24 movlw 3 ; do nibbleshift if bexp >= 4 cpfsgt bexp goto aloop24 subwf bexp ; bexp = bexp -3 swapf barg+b1,w movpf wreg,acc+b4 ; save for rounding andlw 0x0f movpf wreg,barg+b1 swapf barg+b0,w andlw 0xf0 addwf barg+b1 swapf barg+b0,w andlw 0x0f movpf wreg,barg+b0 rlcf acc+b4 ; rotate next bit for rounding dcfsnz bexp ; bexp = bexp - 1 goto around24 ; aligned if bexp = 0 aloop24 bcf _c ; right shift by bexp rrcf barg+b0 rrcf barg+b1 dcfsnz bexp goto around24 ; aligned if bexp = 0 bcf _c rrcf barg+b0 rrcf barg+b1 dcfsnz bexp goto around24 ; aligned if bexp = 0 bcf _c ; at most 3 right shifts are rrcf barg+b0 ; possible rrcf barg+b1 around24 btfsc fpflags,rnd btfss barg+b1,lsb goto aligned24 clrf wreg addwfc barg+b1 ; add carry for rounding addwfc barg+b0 btfss _c ; has rounding caused carryout? goto aligned24 rrcf barg+b0 ; if so, right shift rrcf barg+b1 5-51 www.datasheet.co.kr datasheet pdf - http://www..net/ ds00575a-page 42 ? 1994 microchip technology inc. ieee 754 compliant floating-point routines infsnz exp ; test for floating point overflow goto setfov24 aligned24 btfss temp,msb ; negate if signs opposite goto aok24 comf barg+b1 comf barg+b0 infsnz barg+b1 incf barg+b0 aok24 movfp barg+b1,wreg ; add addwf aarg+b1 movfp barg+b0,wreg addwfc aarg+b0 btfsc temp,msb goto acomp24 btfss _c goto fixsign24 rrcf aarg+b0 ; shift right and increment exp rrcf aarg+b1 incfsz aexp goto fixsign24 goto setfov24 ; set floating point overflow flag acomp24 btfsc _c goto nrm24 ; normalize and fix sign comf aarg+b1 ; negate, toggle sign bit and comf aarg+b0 ; then normalize infsnz aarg+b1 incf aarg+b0 btg sign,msb goto nrm24 end 5-52 www.datasheet.co.kr datasheet pdf - http://www..net/ ? 1994 microchip technology inc. ds00575a-page 43 ieee 754 compliant floating-point routines 5 appendix c ; pic16 32 bit floating point library version 1.14 ; unary operations: both input and output are in aexp,aarg ; binary operations: input in aexp,aarg and bexp,barg with output in aexp,aarg ; all routines return wreg = 0x00 for successful completion, and wreg = 0xff ; for an error condition specified in fpflags. ; all timings are worst case cycle counts ; routine function ; flo32 24 bit integer to 32 bit floating point conversion ; timing: rnd ; 0 1 ; 0 104 104 ; sat ; 1 110 110 ; nrm32 normalization of unnormalized 32 bit floating point numbers ; timing: rnd ; 0 1 ; 0 90 90 ; sat ; 1 96 96 ; int32 32 bit floating point to 24 bit integer conversion ; timing: rnd ; 0 1 ; 0 90 98 ; sat ; 1 90 100 ; fpa32 32 bit floating point add ; timing: rnd ; 0 1 ; 0 248 262 ; sat ; 1 248 268 ; fps32 32 bit floating point subtract ; timing: rnd ; 0 1 ; 0 250 264 ; sat ; 1 250 270 ; fpm32 32 bit floating point multiply ; timing: rnd ; 0 1 ; 0 574 588 5-53 www.datasheet.co.kr datasheet pdf - http://www..net/ ds00575a-page 44 ? 1994 microchip technology inc. ieee 754 compliant floating-point routines ; sat ; 1 574 591 ; fpd32 32 bit floating point divide ; timing: rnd ; 0 1 ; 0 929 965 ; sat ; 1 929 968 list r=dec,x=on,t=off,p=16c71 include ? 1994 microchip technology inc. ds00575a-page 45 ieee 754 compliant floating-point routines 5 ; define floating point library exception flags fpflags equ 0x14 ; floating point library exception flags iov equ 0 ; bit0 = integer overflow flag fov equ 1 ; bit1 = floating point overflow flag fun equ 2 ; bit2 = floating point underflow flag fdz equ 3 ; bit3 = floating point divide by zero flag rnd equ 6 ; bit6 = floating point rounding flag, 0 = truncation ; 1 = rounding to nearest lsb sat equ 7 ; bit7 = floating point saturate flag, 0 = terminate on ; exception without saturation, 1 = terminate on ; exception with saturation to appropriate value ;********************************************************************************************** ;********************************************************************************************** ; integer to float conversion ; input: 24 bit 2s complement integer right justified in aarg+b0, aarg+b1, ; aarg+b2 ; use: call flo32 ; output: 32 bit floating point number in aexp, aarg+b0, aarg+b1, aarg+b2 ; result: aarg < float( aarg ) ; max timing: 14+90 = 104 clks sat = 0 ; 14+96 = 110 clks sat = 1 ; min timing: 6+28 = 34 clks aarg = 0 ; 6+18 = 24 clks ; pm: 14+38 = 52 dm: 7 flo32 movlw 24+expbias ; initialize exponent and add bias movwf exp clrf sign btfss acc+b0,msb ; test sign goto nrm32 comf acc+b2 ; if < 0, negate and set msb in sign comf acc+b1 comf acc+b0 incf acc+b2 btfsc _z incf acc+b1 btfsc _z incf acc+b0 bsf sign,msb ; ; normalization routine ; input: 32 bit unnormalized floating point number in aexp, aarg+b0, aarg+b1, ; aarg+b2, with sign in sign,msb ; use: call nrm32 ; output: 32 bit normalized floating point number in aexp, aarg+b0, aarg+b1, ; aarg+b2 5-55 www.datasheet.co.kr datasheet pdf - http://www..net/ ds00575a-page 46 ? 1994 microchip technology inc. ieee 754 compliant floating-point routines ; result: aarg < normalize( aarg ) ; max timing: 21+6+7*8+7 = 90 clks sat = 0 ; 21+6+7*8+1+12 = 96 clks sat = 1 ; min timing: 22+6 = 28 clks aarg = 0 ; 5+9+4 = 18 clks ; pm: 38 dm: 7 nrm32 clrf temp ; clear exponent decrement movf acc+b0,w ; test if highbyte=0 btfss _z goto norm32 movf acc+b1,w ; if so, shift 8 bits by move movwf acc+b0 movf acc+b2,w movwf acc+b1 clrf acc+b2 bsf temp,3 ; increase decrement by 8 movf acc+b0,w ; test if highbyte=0 btfss _z goto norm32 movf acc+b1,w ; if so, shift 8 bits by move movwf acc+b0 clrf acc+b1 bcf temp,3 ; increase decrement by 8 bsf temp,4 movf acc+b0,w ; if highbyte=0, result=0 btfsc _z goto res032 norm32 movf temp,w subwf exp btfss _z btfss _c goto setfun32 bcf _c ; clear carry bit norm32a btfsc acc+b0,msb ; if msb=1, normalization done goto fixsign32 rlf acc+b2 ; otherwise, shift left and rlf acc+b1 ; decrement exp rlf acc+b0 decfsz exp goto norm32a goto setfun32 ; underflow if exp=0 fixsign32 btfss sign,msb bcf acc+b0,msb ; clear explicit msb if positive retlw 0 ;********************************************************************************************** ;********************************************************************************************** ; float to integer conversion ; input: 32 bit floating point number in aexp, aarg+b0, aarg+b1, aarg+b2 ; use: call int32 ; output: 24 bit 2s complement integer right justified in aarg+b0, aarg+b1, ; aarg+b2 5-56 www.datasheet.co.kr datasheet pdf - http://www..net/ ? 1994 microchip technology inc. ds00575a-page 47 ieee 754 compliant floating-point routines 5 ; result: aarg < int( aarg ) ; max timing: 26+6*7+6+16 = 90 clks rnd = 0 ; 26+6*7+6+24 = 98 clks rnd = 1, sat = 0 ; 26+6*7+6+26 = 100 clks rnd = 1, sat = 1 ; min timing: 9+6 = 15 clks aarg = 0 ; 19+6+7 = 32 clks ; pm: 83 dm: 6 int32 movf acc+b0,w ; save sign in sign movwf sign bsf acc+b0,msb ; make msb explicit movlw expbias ; remove bias from exp subwf exp btfss exp,msb ; if <= 0, result=0 btfsc _z goto res032 movf exp,w sublw 24 movwf exp btfss _z btfsc exp,msb goto setiov32 movlw 8 ; do byte shift if exp >= 8 subwf exp,w btfss _c goto shift32 movwf exp rlf acc+b2 ; rotate next bit for rounding movf acc+b1,w movwf acc+b2 movf acc+b0,w movwf acc+b1 clrf acc+b0 movlw 8 ; do another byte shift if exp >= 8 subwf exp,w btfss _c goto shift32 movwf exp rlf acc+b2 ; rotate next bit for rounding movf acc+b1,w movwf acc+b2 clrf acc+b1 movf exp,w ; shift completed if exp = 0 btfsc _z goto shift32ok shift32 bcf _c rrf acc+b0 ; right shift by exp rrf acc+b1 rrf acc+b2 decfsz exp goto shift32 shift32ok btfsc fpflags,rnd btfss acc+b2,lsb goto int32ok btfss _c goto int32ok incf acc+b2 btfsc _z incf acc+b1 5-57 www.datasheet.co.kr datasheet pdf - http://www..net/ ds00575a-page 48 ? 1994 microchip technology inc. ieee 754 compliant floating-point routines btfsc _z incf acc+b0 btfsc acc+b0,msb ; test for overflow goto setiov32 int32ok btfss sign,msb ; if sign bit set, negate retlw 0 comf acc+b0 comf acc+b1 comf acc+b2 incf acc+b2 btfsc _z incf acc+b1 btfsc _z incf acc+b0 retlw 0 res032 clrf acc+b0 ; integer result equals zero clrf acc+b1 clrf acc+b2 clrf exp ; clear exp for other routines retlw 0 setiov32 bsf fpflags,iov ; set integer overflow flag btfss fpflags,sat ; test for saturation retlw 0xff ; return error code in wreg clrf acc+b0 ; saturate to largest twos btfss sign,msb ; complement 16 bit integer movlw 0xff movwf acc+b0 ; sign = 0, 0x 7f ff ff movwf acc+b1 ; sign = 1, 0x 80 00 00 movwf acc+b2 rlf sign rrf acc+b0 retlw 0xff ; return error code in wreg ;********************************************************************************************** ;********************************************************************************************** ; floating point multiply ; input: 32 bit floating point number in aexp, aarg+b0, aarg+b1, aarg+b2 ; 32 bit floating point number in bexp, barg+b0, barg+b1, barg+b2 ; use: call fpm32 ; output: 32 bit floating point product in aexp, aarg+b0, aarg+b1, aarg+b2 ; result: aarg < aarg * barg ; max timing: 26+23*22+21+21 = 574 clks rnd = 0 ; 26+23*22+21+35 = 588 clks rnd = 1, sat = 0 ; 26+23*22+21+38 = 591 clks rnd = 1, sat = 1 ; min timing: 6+6 = 12 clks aarg * barg = 0 ; 24+23*11+21+17 = 315 clks ; pm: 94 dm: 14 fpm32 movf aexp,w ; test for zero arguments btfss _z movf bexp,w btfsc _z goto res032 m32bne0 movf aarg+b0,w 5-58 www.datasheet.co.kr datasheet pdf - http://www..net/ ? 1994 microchip technology inc. ds00575a-page 49 ieee 754 compliant floating-point routines 5 xorwf barg+b0,w movwf sign ; save sign in sign movf bexp,w addwf exp movlw expbias btfss _c goto mtun32 addwf exp btfsc _c goto setfov32 ; set multiply overflow flag goto mok32 mtun32 addwf exp btfss _c goto setfun32 mok32 bsf aarg+b0,msb ; make argument msbs explicit bsf barg+b0,msb bcf _c clrf acc+b3 ; clear initial partial product clrf acc+b4 clrf acc+b5 movlw 24 movwf temp ; initialize counter mloop32 btfss aarg+b2,lsb ; test high byte goto mnoadd32 madd32 movf barg+b2,w addwf acc+b5 movf barg+b1,w btfsc _c incfsz barg+b1,w addwf acc+b4 movf barg+b0,w btfsc _c incfsz barg+b0,w addwf acc+b3 mnoadd32 rrf acc+b3 rrf acc+b4 rrf acc+b5 rrf acc+b0 rrf acc+b1 rrf acc+b2 bcf _c decfsz temp goto mloop32 btfsc acc+b3,msb ; check for postnormalization goto mround32 rlf acc+b0 rlf acc+b5 rlf acc+b4 rlf acc+b3 decf exp mround32 btfsc fpflags,rnd btfss acc+b5,lsb goto mul32ok rlf acc+b0 ; rotate next significant bit into btfsc _c incf acc+b5 ; carry for rounding btfsc _z incf acc+b4 btfsc _z 5-59 www.datasheet.co.kr datasheet pdf - http://www..net/ ds00575a-page 50 ? 1994 microchip technology inc. ieee 754 compliant floating-point routines incf acc+b3 btfss _c ; has rounding caused carryout? goto mul32ok rrf acc+b3 ; if so, right shift rrf acc+b4 rrf acc+b5 incf exp btfsc _c ; check for overflow goto setfov32 mul32ok btfss sign,msb bcf acc+b3,msb ; clear explicit msb if positive movf acc+b3,w movwf aarg+b0 ; move result to aarg movf acc+b4,w movwf aarg+b1 movf acc+b5,w movwf aarg+b2 retlw 0 setfov32 bsf fpflags,fov ; set floating point underflag btfss fpflags,sat ; test for saturation retlw 0xff ; return error code in wreg movlw 0xff movwf aexp ; saturate to largest floating movwf aarg+b0 ; point number = 0x ff 7f ff ff movwf aarg+b1 ; modulo the appropriate sign bit movwf aarg+b2 rlf sign rrf aarg+b0 retlw 0xff ; return error code in wreg ;********************************************************************************************** ;********************************************************************************************** ; floating point divide ; input: 32 bit floating point dividend in aexp, aarg+b0, aarg+b1, aarg+b2 ; 32 bit floating point divisor in bexp, barg+b0, barg+b1, barg+b2 ; use: call fpd32 ; output: 32 bit floating point quotient in aexp, aarg+b0, aarg+b1, aarg+b2 ; result: aarg < aarg / barg ; max timing: 40+12+23*36+35+14 = 929 clks rnd = 0 ; 40+12+23*36+35+50 = 965 clks rnd = 1, sat = 0 ; 40+12+23*36+35+53 = 968 clks rnd = 1, sat = 1 ; min timing: 31+12+23*27+26+14 = 704 clks ; pm: 152 dm: 14 fpd32 movf bexp,w ; test for divide by zero btfsc _z goto setfdz32 d32bne0 movf aarg+b0,w xorwf barg+b0,w movwf sign ; save sign in sign bsf aarg+b0,msb ; make argument msbs explicit bsf barg+b0,msb talign32 clrf temp ; clear align increment movf aarg+b0,w 5-60 www.datasheet.co.kr datasheet pdf - http://www..net/ ? 1994 microchip technology inc. ds00575a-page 51 ieee 754 compliant floating-point routines 5 movwf acc+b3 ; test for alignment movf aarg+b1,w movwf acc+b4 movf aarg+b2,w movwf acc+b5 movf barg+b2,w subwf acc+b5 movf barg+b1,w btfss _c incfsz barg+b1,w ts1align32 subwf acc+b4 movf barg+b0,w btfss _c incfsz barg+b0,w ts2align32 subwf acc+b3 clrf acc+b3 clrf acc+b4 clrf acc+b5 btfss _c goto dalign32ok bcf _c ; align if necessary rrf acc+b0 rrf acc+b1 rrf acc+b2 rrf acc+b3 movlw 0x01 movwf temp ; save align increment dalign32ok movf bexp,w ; compare aexp and bexp subwf exp btfss _c goto altb32 ageb32 movlw expbias addwf temp,w addwf exp btfsc _c goto setfov32 goto dargok32 ; set overflow flag altb32 movlw expbias addwf temp,w addwf exp btfss _c goto setfun32 ; set underflow flag dargok32 movlw 24 ; initialize counter movwf temp+b1 dloop32 rlf acc+b5 ; left shift rlf acc+b4 rlf acc+b3 rlf acc+b2 rlf acc+b1 rlf acc+b0 rlf temp movf barg+b2,w ; subtract subwf acc+b2 movf barg+b1,w btfss _c incfsz barg+b1,w ds132 subwf acc+b1 5-61 www.datasheet.co.kr datasheet pdf - http://www..net/ ds00575a-page 52 ? 1994 microchip technology inc. ieee 754 compliant floating-point routines movf barg+b0,w btfss _c incfsz barg+b0,w ds232 subwf acc+b0 rlf barg+b0,w iorwf temp btfss temp,lsb ; test for restore goto drest32 bsf acc+b5,lsb goto dok32 drest32 movf barg+b2,w ; restore if necessary addwf acc+b2 movf barg+b1,w btfsc _c incfsz barg+b1,w darest32 addwf acc+b1 movf barg+b0,w btfsc _c incf barg+b0,w addwf acc+b0 bcf acc+b5,lsb dok32 decfsz temp+b1 goto dloop32 dround32 btfsc fpflags,rnd btfss acc+b5,lsb goto div32ok bcf _c rlf acc+b2 ; compute next significant bit rlf acc+b1 ; for rounding rlf acc+b0 rlf temp movf barg+b2,w ; subtract subwf acc+b2 movf barg+b1,w btfss _c incfsz barg+b1,w goto ds1round32 bsf _c btfss _c ds1round32 subwf acc+b1 movf barg+b0,w btfss _c incfsz barg+b0,w goto ds2round32 bsf _c btfss _c ds2round32 subwf acc+b0 rlf barg+b0,w iorwf temp,w andlw 0x01 addwf acc+b5 btfsc _c incf acc+b4 btfsc _z incf acc+b3 5-62 www.datasheet.co.kr datasheet pdf - http://www..net/ ? 1994 microchip technology inc. ds00575a-page 53 ieee 754 compliant floating-point routines 5 btfss _z ; test if rounding caused carryout goto div32ok rrf acc+b3 rrf acc+b4 rrf acc+b5 incf exp btfsc _z ; test for overflow goto setfov32 div32ok btfss sign,msb bcf acc+b3,msb ; clear explicit msb if positive movf acc+b3,w movwf aarg+b0 ; move result to aarg movf acc+b4,w movwf aarg+b1 movf acc+b5,w movwf aarg+b2 retlw 0 setfun32 bsf fpflags,fun ; set floating point underflag btfss fpflags,sat ; test for saturation retlw 0xff ; return error code in wreg movlw 0x01 ; saturate to smallest floating movwf aexp ; point number = 0x 01 00 00 00 clrf aarg+b0 ; modulo the appropriate sign bit clrf aarg+b1 clrf aarg+b2 rlf sign rrf aarg+b0 retlw 0xff ; return error code in wreg setfdz32 bsf fpflags,fdz ; set divide by zero flag retlw 0xff ;********************************************************************************************** ;********************************************************************************************** ; floating point subtract ; input: 32 bit floating point number in aexp, aarg+b0, aarg+b1, aarg+b2 ; 32 bit floating point number in bexp, barg+b0, barg+b1, barg+b2 ; use: call fps32 ; output: 32 bit floating point sum in aexp, aarg+b0, aarg+b1, aarg+b2 ; result: aarg < aarg - barg ; max timing: 2+248 = 250 clks rnd = 0 ; 2+262 = 264 clks rnd = 1, sat = 0 ; 2+268 = 270 clks rnd = 1, sat = 1 ; min timing: 2+50 = 52 clks ; pm: 2+136 = 138 dm: 14 fps32 movlw 0x80 xorwf barg+b0 ; ; floating point add ; input: 32 bit floating point number in aexp, aarg+b0, aarg+b1, aarg+b2 ; 32 bit floating point number in bexp, barg+b0, barg+b1, barg+b2 5-63 www.datasheet.co.kr datasheet pdf - http://www..net/ ds00575a-page 54 ? 1994 microchip technology inc. ieee 754 compliant floating-point routines ; use: call fpa32 ; output: 32 bit floating point sum in aexp, aarg+b0, aarg+b1, aarg+b2 ; result: aarg < aarg - barg ; max timing: 31+38+6*7+6+41+90 = 248 clks rnd = 0 ; 31+38+6*7+6+55+90 = 262 clks rnd = 1, sat = 0 ; 31+38+6*7+6+55+96 = 268 clks rnd = 1, sat = 1 ; min timing: 8+38+4 = 50 clks ; pm: 136 dm: 14 fpa32 movf aarg+b0,w ; exclusive or of signs in temp xorwf barg+b0,w movwf temp movf aexp,w ; use aarg if aexp >= bexp subwf bexp,w btfss _c goto usea32 movf bexp,w movwf acc+b5 ; otherwise, swap aarg and barg movf aexp,w movwf bexp movf acc+b5,w movwf aexp movf barg+b0,w movwf acc+b5 movf aarg+b0,w movwf barg+b0 movf acc+b5,w movwf aarg+b0 movf barg+b1,w movwf acc+b5 movf aarg+b1,w movwf barg+b1 movf acc+b5,w movwf aarg+b1 movf barg+b2,w movwf acc+b5 movf aarg+b2,w movwf barg+b2 movf acc+b5,w movwf aarg+b2 usea32 movf aarg+b0,w movwf sign ; save sign in sign bsf aarg+b0,msb ; make msbs explicit bsf barg+b0,msb movf barg+b0,w movwf acc+b3 movf barg+b1,w movwf acc+b4 movf barg+b2,w movwf acc+b5 movf bexp,w ; compute shift count in bexp subwf aexp,w movwf bexp btfsc _z goto around32 5-64 www.datasheet.co.kr datasheet pdf - http://www..net/ ? 1994 microchip technology inc. ds00575a-page 55 ieee 754 compliant floating-point routines 5 movlw 8 subwf bexp,w btfss _c ; if bexp >= 8, do byte shift goto alignb32 movwf bexp rlf acc+b5 ; rotate next bit for rounding movf acc+b4,w movwf acc+b5 movf acc+b3,w movwf acc+b4 clrf acc+b3 movlw 8 subwf bexp,w btfss _c ; if bexp >= 8, do byte shift goto alignb32 movwf bexp rlf acc+b5 ; rotate next bit for rounding movf acc+b4,w movwf acc+b5 clrf acc+b4 alignb32 movf bexp,w ; already aligned if bexp = 0 btfsc _z goto around32 aloopb32 bcf _c ; right shift by bexp rrf acc+b3 rrf acc+b4 rrf acc+b5 decfsz bexp goto aloopb32 around32 btfsc fpflags,rnd btfss acc+b5,lsb goto aligned32 btfss _c goto aligned32 incf acc+b5 btfsc _z incf acc+b4 btfsc _z incf acc+b3 btfss _z goto aligned32 rrf acc+b3 rrf acc+b4 rrf acc+b5 incf exp btfsc _z goto setfov32 aligned32 btfss temp,msb ; negate if signs opposite goto aok32 comf acc+b3 comf acc+b4 comf acc+b5 incf acc+b5 btfsc _z incf acc+b4 btfsc _z incf acc+b3 aok32 movf acc+b5,w ; add 5-65 www.datasheet.co.kr datasheet pdf - http://www..net/ ds00575a-page 56 ? 1994 microchip technology inc. ieee 754 compliant floating-point routines addwf aarg+b2 movf acc+b4,w btfsc _c incfsz acc+b4,w addwf aarg+b1 movf acc+b3,w btfsc _c incfsz acc+b3,w addwf aarg+b0 btfsc temp,msb goto acomp32 btfss _c goto fixsign32 rrf aarg+b0 ; shift right and increment exp rrf aarg+b1 rrf aarg+b2 incfsz aexp goto fixsign32 goto setfov32 acomp32 btfsc _c goto nrm32 ; normalize and fix sign comf aarg+b0 ; negate, toggle sign bit and comf aarg+b1 ; then normalize comf aarg+b2 incf aarg+b2 btfsc _z incf aarg+b1 btfsc _z incf aarg+b0 movlw 0x80 xorwf sign goto nrm32 end 5-66 www.datasheet.co.kr datasheet pdf - http://www..net/ ? 1994 microchip technology inc. ds00575a-page 57 ieee 754 compliant floating-point routines 5 appendix d ; pic17 32 bit floating point library version 1.14 ; unary operations: both input and output are in aexp,aarg ; binary operations: input in aexp,aarg and bexp,barg with output in aexp,aarg ; all routines return wreg = 0x00 for successful completion, and wreg = 0xff ; for an error condition specified in fpflags. ; max timings are worst case cycle counts, while min timings are non-exception ; best case cycle counts. ; routine function ; flo24 16 bit integer to 24 bit floating point conversion ; timing: rnd ; 0 1 ; 0 60 60 ; sat ; 1 67 67 ; nrm24 normalization of unnormalized 24 bit floating point numbers ; timing: rnd ; 0 1 ; 0 48 48 ; sat ; 1 55 55 ; int24 24 bit floating point to 16 bit integer conversion ; timing: rnd ; 0 1 ; 0 69 73 ; sat ; 1 69 76 ; fpa24 24 bit floating point add ; timing: rnd ; 0 1 ; 0 144 159 ; sat ; 1 144 159 ; fps24 24 bit floating point subtract ; timing: rnd ; 0 1 ; 0 145 160 ; sat ; 1 145 160 ; fpm24 24 bit floating point multiply ; timing: rnd ; 0 1 ; 0 320 331 5-67 www.datasheet.co.kr datasheet pdf - http://www..net/ ds00575a-page 58 ? 1994 microchip technology inc. ieee 754 compliant floating-point routines ; sat ; 1 320 336 ; fpd24 24 bit floating point divide ; timing: rnd ; 0 1 ; 0 597 621 ; sat ; 1 597 627 list r=dec,x=on,t=off,p=17c42 include ? 1994 microchip technology inc. ds00575a-page 59 ieee 754 compliant floating-point routines 5 ; define floating point library exception flags fpflags equ 0x20 ; floating point library exception flags iov equ 0 ; bit0 = integer overflow flag fov equ 1 ; bit1 = floating point overflow flag fun equ 2 ; bit2 = floating point underflow flag fdz equ 3 ; bit3 = floating point divide by zero flag rnd equ 6 ; bit6 = floating point rounding flag, 0 = truncation ; 1 = rounding to nearest lsb sat equ 7 ; bit7 = floating point saturate flag, 0 = terminate on ; exception without saturation, 1 = terminate on ; exception with saturation to appropriate value ;********************************************************************************************** ;********************************************************************************************** ; integer to float conversion ; input: 24 bit 2s complement integer right justified in aarg+b0,aarg+b1, ; aarg+b2 ; use: call flo32 ; output: 32 bit floating point number in aexp, aarg+b0, aarg+b1, aarg+b2 ; result: aarg < float( aarg ) ; max timing: 12+48 = 60 clks sat = 0 ; 12+55 = 67 clks sat = 1 ; min timing: 6+24 = 30 clks aarg = 0 ; 6+20 = 26 clks ; pm: 12+108 = 120 dm: 7 flo32 movlw 24+expbias ; initialize exponent and add bias movwf exp movfp acc+b0,sign ; save sign in sign btfss acc+b0,msb ; test sign goto nrm32 clrf wreg ; if < 0, negate, set msb in sign comf acc+b2 comf acc+b1 comf acc+b0 incf acc+b2 addwfc acc+b1 addwfc acc+b0 ; ; normalization routine ; input: 32 bit unnormalized floating point number in aexp, aarg+b0, aarg+b1, ; aarg+b2 with sign in sign,msb. ; use: call nrm32 ; output: 32 bit normalized floating point number in aexp, aarg+b0, aarg+b1, ; aarg+b2 ; result: aarg < normalize( aarg ) ; max timing: 21+19+8 = 48 clks sat = 0 5-69 www.datasheet.co.kr datasheet pdf - http://www..net/ ds00575a-page 60 ? 1994 microchip technology inc. ieee 754 compliant floating-point routines ; 21+19+15 = 55 clks sat = 1 ; min timing: 4+7+7+6 = 24 clks aarg = 0 ; 3+5+4+8 = 20 clks ; pm: 108 dm: 7 nrm32 clrf temp,w ; clear exponent decrement cpfsgt acc+b0 ; test if highbyte=0 goto nrm32a tnib32 movlw 0xf0 ; test if highnibble=0 andwf acc+b0,w tstfsz wreg goto norm32 swapf acc+b0 ; if so, shift 4 bits swapf acc+b1,w andlw 0x0f addwf acc+b0 swapf acc+b1,w andlw 0xf0 movpf wreg,acc+b1 swapf acc+b2,w andlw 0x0f addwf acc+b1 swapf acc+b2,w andlw 0xf0 movpf wreg,acc+b2 bsf temp,2 ; increase decrement by 4 norm32 bcf _c ; clear carry bit btfsc acc+b0,msb ; if msb=1, normalization done goto tnormun32 rlcf acc+b2 ; otherwise, shift left and rlcf acc+b1 ; increment decrement rlcf acc+b0 incf temp btfsc acc+b0,msb goto tnormun32 rlcf acc+b2 rlcf acc+b1 rlcf acc+b0 incf temp btfsc acc+b0,msb ; since highnibble != 0, at most goto tnormun32 ; 3 left shifts are required rlcf acc+b2 rlcf acc+b1 rlcf acc+b0 incf temp tnormun32 movfp temp,wreg ; if exp <= decrement in temp, cpfsgt exp ; floating point underflow has goto setfun32 ; occured subwf exp ; otherwise, compute exp fixsign32 btfss sign,msb bcf acc+b0,msb ; clear explicit msb if positive retlw 0 nrm32a movfp acc+b1,acc+b0 ; shift 8 bits by move movfp acc+b2,acc+b1 clrf acc+b2,w bsf temp,3 ; increase decrement by 8 cpfsgt acc+b0 ; test if highbyte=0 goto nrm32b 5-70 www.datasheet.co.kr datasheet pdf - http://www..net/ ? 1994 microchip technology inc. ds00575a-page 61 ieee 754 compliant floating-point routines 5 tnib32a movlw 0xf0 ; test if highnibble=0 andwf acc+b0,w tstfsz wreg goto norm32a swapf acc+b0 ; if so, shift 4 bits swapf acc+b1,w andlw 0x0f addwf acc+b0 swapf acc+b1,w andlw 0xf0 movpf wreg,acc+b1 bsf temp,2 ; increase decrement by 4 norm32a bcf _c ; clear carry bit btfsc acc+b0,msb ; if msb=1, normalization done goto tnormun32 rlcf acc+b1 ; otherwise, shift left and rlcf acc+b0 ; increment decrement incf temp btfsc acc+b0,msb goto tnormun32 rlcf acc+b1 rlcf acc+b0 incf temp btfsc acc+b0,msb ; since highnibble != 0, at most goto tnormun32 ; 3 left shifts are required rlcf acc+b1 rlcf acc+b0 incf temp goto tnormun32 nrm32b movfp acc+b1,acc+b0 ; shift 8 bits by move clrf acc+b1,w bcf temp,3 ; increase decrement by 8 bsf temp,4 cpfsgt acc+b0 ; if highbyte=0, result=0 goto res032 tnib32b movlw 0xf0 ; test if highnibble=0 andwf acc+b0,w tstfsz wreg goto norm32b swapf acc+b0 ; if so, shift 4 bits bsf temp,2 ; increase decrement by 4 norm32b bcf _c ; clear carry bit btfsc acc+b0,msb ; if msb=1, normalization done goto tnormun32 rlcf acc+b0 ; otherwise, shift left and incf temp ; increment decrement btfsc acc+b0,msb goto tnormun32 rlcf acc+b0 incf temp btfsc acc+b0,msb ; since highnibble != 0, at most goto tnormun32 ; 3 left shifts are required rlcf acc+b0 incf temp goto tnormun32 ;********************************************************************************************** ;********************************************************************************************** 5-71 www.datasheet.co.kr datasheet pdf - http://www..net/ ds00575a-page 62 ? 1994 microchip technology inc. ieee 754 compliant floating-point routines ; float to integer conversion ; input: 32 bit floating point number in aexp, aarg+b0, aarg+b1, aarg+b2 ; use: call int32 ; output: 24 bit 2s complement integer right justified in aarg+b0, aarg+b1, ; aarg+b2 ; result: aarg < int( aarg ) ; max timing: 11+43+15 = 69 clks rnd = 0 ; 11+43+19 = 73 clks rnd = 1, sat = 0 ; 11+43+22 = 76 clks rnd = 1, sat = 1 ; min timing: 6+6 = 12 clks aarg = 0 ; 11+11+8 = 30 clks ; pm: 155 dm: 7 int32 movfp acc+b0,sign ; save sign in sign bsf acc+b0,msb ; make msb explicit movlw expbias ; remove bias from exp cpfsgt exp ; if <= 0, result=0 goto res032 subwf exp movlw 24 cpfslt exp ; if >= 16, integer overflow goto setiov32 ; will occur subwf exp,w negw exp movlw 7 ; do byte shift if exp >= 8 cpfsgt exp goto snib32 subwf exp ; exp = exp - 7 rlcf acc+b2 ; rotate next bit for rounding movfp acc+b1,acc+b2 movfp acc+b0,acc+b1 clrf acc+b0 dcfsnz exp ; exp = exp - 1 goto shift32ok ; shift completed if exp = 0 cpfsgt exp ; do another byte shift if exp >= 8 goto snib32a subwf exp ; exp = exp - 7 rlcf acc+b2 ; rotate next bit for rounding movfp acc+b1,acc+b2 clrf acc+b1 dcfsnz exp ; exp = exp - 1 goto shift32ok ; shift completed if exp = 0 snib32b movlw 3 ; do nibble shift if exp >= 4 cpfsgt exp goto shift32b subwf exp ; exp = exp - 3 swapf acc+b2,w movpf wreg,acc+b3 ; save for rounding andlw 0x0f movpf wreg,acc+b2 rlcf acc+b3 ; rotate next bit for rounding dcfsnz exp ; exp = exp - 1 goto shift32ok ; shift completed if exp = 0 shift32b bcf _c ; at most 3 right shifts are required 5-72 www.datasheet.co.kr datasheet pdf - http://www..net/ ? 1994 microchip technology inc. ds00575a-page 63 ieee 754 compliant floating-point routines 5 rrcf acc+b2 ; right shift by exp dcfsnz exp goto shift32ok ; shift completed if exp = 0 bcf _c rrcf acc+b2 dcfsnz exp goto shift32ok ; shift completed if exp = 0 bcf _c rrcf acc+b2 goto shift32ok snib32a movlw 3 ; do nibble shift if exp >= 4 cpfsgt exp goto shift32a subwf exp ; exp = exp - 3 swapf acc+b2,w movpf wreg,acc+b3 ; save for rounding andlw 0x0f movpf wreg,acc+b2 swapf acc+b1,w andlw 0xf0 addwf acc+b2 swapf acc+b1,w andlw 0x0f movpf wreg,acc+b1 rlcf acc+b3 ; rotate next bit for rounding dcfsnz exp ; exp = exp - 1 goto shift32ok ; shift completed if exp = 0 shift32a bcf _c ; at most 3 right shifts are required rrcf acc+b1 ; right shift by exp rrcf acc+b2 dcfsnz exp goto shift32ok ; shift completed if exp = 0 bcf _c rrcf acc+b1 rrcf acc+b2 dcfsnz exp goto shift32ok ; shift completed if exp = 0 bcf _c rrcf acc+b1 rrcf acc+b2 goto shift32ok snib32 movlw 3 ; do nibble shift if exp >= 4 cpfsgt exp goto shift32 subwf exp ; exp = exp - 3 swapf acc+b2,w movpf wreg,acc+b3 ; save for rounding andlw 0x0f movpf wreg,acc+b2 swapf acc+b1,w andlw 0xf0 addwf acc+b2 swapf acc+b1,w andlw 0x0f movpf wreg,acc+b1 swapf acc+b0,w andlw 0xf0 addwf acc+b1 swapf acc+b0,w 5-73 www.datasheet.co.kr datasheet pdf - http://www..net/ ds00575a-page 64 ? 1994 microchip technology inc. ieee 754 compliant floating-point routines andlw 0x0f movpf wreg,acc+b0 rlcf acc+b3 ; rotate next bit for rounding dcfsnz exp ; exp = exp - 1 goto shift32ok ; shift completed if exp = 0 shift32 bcf _c ; at most 3 right shifts are required rrcf acc+b0 ; right shift by exp rrcf acc+b1 rrcf acc+b2 dcfsnz exp goto shift32ok ; shift completed if exp = 0 bcf _c rrcf acc+b0 rrcf acc+b1 rrcf acc+b2 dcfsnz exp goto shift32ok ; shift completed if exp = 0 bcf _c rrcf acc+b0 rrcf acc+b1 rrcf acc+b2 shift32ok clrf wreg btfsc fpflags,rnd btfss acc+b2,lsb goto int32ok addwfc acc+b2 ; add next bit for rounding addwfc acc+b1 addwfc acc+b0 btfsc acc+b0,msb goto setiov32 int32ok btfss sign,msb ; if sign bit set, negate retlw 0 comf acc+b2 comf acc+b1 comf acc+b0 incf acc+b2 addwfc acc+b1 addwfc acc+b0 retlw 0 res032 clrf acc+b0 ; integer result equals zero clrf acc+b1 clrf acc+b2 clrf exp ; clear exponent for other routines retlw 0 setiov32 bsf fpflags,iov ; set integer overflow flag btfss fpflags,sat ; test for saturation retlw 0xff ; return error code in wreg clrf acc+b0 ; saturate to largest twos btfss sign,msb ; complement 24 bit integer setf acc+b0 ; sign = 0, 0x 7f ff ff movpf acc+b0,acc+b1 ; sign = 1, 0x 80 00 00 movpf acc+b0,acc+b2 rlcf sign rrcf acc+b0 retlw 0xff ; return error code in wreg ;********************************************************************************************** ;********************************************************************************************** ; floating point multiply ; input: 32 bit floating point number in aexp, aarg+b0, aarg+b1, aarg+b2 5-74 www.datasheet.co.kr datasheet pdf - http://www..net/ ? 1994 microchip technology inc. ds00575a-page 65 ieee 754 compliant floating-point routines 5 ; 32 bit floating point number in bexp, barg+b0, barg+b1, barg+b2 ; use: call fpm32 ; output: 32 bit floating point product in aexp, aarg+b0, aarg+b1, aarg+b2 ; result: aarg < aarg * barg ; max timing: 19+283+18 = 320 clks rnd = 0, sat = 0 ; 19+283+29 = 331 clks rnd = 1, sat = 0 ; 19+283+34 = 336 clks rnd = 1, sat = 1 ; min timing: 5+6 = 11 clks aarg * barg = 0 ; 18+54+16 = 88 clks ; pm: 21+322+39 = 382 dm: 13 mul32 macro ; max timing: 13+22*12+6 = 283 clks ; min timing: 4+22*2+6 = 54 clks ; pm: 4+24*2+6+22*12 = 322 dm: 9 variable i = 0 variable j = 1 bcf _c ; clear carry bit clrf acc+b3 ; clear initial partial product clrf acc+b4 clrf acc+b5 while i < 24 if i < 8 btfsc aarg+b2,i ; test low byte endif if i >= 8 && i < 16 btfsc aarg+b1,i-8 ; test middle byte endif goto madd32#v( i ) if i >= 16 btfsc aarg+b0,i-16 ; test high byte endif goto madd32#v( i ) i += 1 endw ; we can not get here since the msbs are explicit madd320 movfp barg+b0,acc+b3 ; if we get here, acc=0 so move movfp barg+b1,acc+b4 ; barg for add movfp barg+b2,acc+b5 rrcf acc+b3 5-75 www.datasheet.co.kr datasheet pdf - http://www..net/ ds00575a-page 66 ? 1994 microchip technology inc. ieee 754 compliant floating-point routines rrcf acc+b4 rrcf acc+b5 while j < 23 if j < 8 btfss aarg+b2,j ; test low byte endif if j >= 8 && j < 16 btfss aarg+b1,j-8 ; test middle byte endif if j >= 16 btfss aarg+b0,j-16 ; test middle byte endif goto mnoadd32#v( j ) madd32#v( j ) movfp barg+b2,wreg addwf acc+b5 ; add low byte movfp barg+b1,wreg addwfc acc+b4 ; add middle byte movfp barg+b0,wreg addwfc acc+b3 ; add high byte mnoadd32#v( j ) rrcf acc+b3 rrcf acc+b4 rrcf acc+b5 if j > 21 rrcf acc+b1 ; save bits for rounding endif if j < 22 bcf _c ; clear carry when rotate possible endif j += 1 endw madd3223 movfp barg+b2,wreg addwf acc+b5 ; add low byte movfp barg+b1,wreg addwfc acc+b4 ; add middle byte movfp barg+b0,wreg addwfc acc+b3 ; add high byte endm fpm32 clrf wreg ; test for zero arguments cpfseq bexp cpfsgt aexp goto res032 m24bne0 movfp aarg+b0,wreg xorwf barg+b0,w 5-76 www.datasheet.co.kr datasheet pdf - http://www..net/ ? 1994 microchip technology inc. ds00575a-page 67 ieee 754 compliant floating-point routines 5 movpf wreg,sign ; save sign in sign movfp bexp,wreg addwf exp movlw expbias btfss _c goto mtun32 addwf exp ; remove bias and overflow test btfsc _c goto setfov32 goto mok32 mtun32 addwf exp ; remove bias and underflow test btfss _c goto setfun32 mok32 bsf aarg+b0,msb ; make argument msbs explicit bsf barg+b0,msb mul32 ; use macro for multiplication btfsc _c ; check for postnormalization goto mright32 decf exp goto mround32 mright32 rrcf acc+b3 rrcf acc+b4 rrcf acc+b5 rrcf acc+b1 mround32 btfsc fpflags,rnd btfss acc+b5,lsb goto mul32ok clrf wreg rlcf acc+b1 ; rotate next significant bit into addwfc acc+b5 ; carry for rounding addwfc acc+b4 addwfc acc+b3 btfss _c ; has rounding caused carryout? goto mul32ok rrcf acc+b3 ; if so, right shift rrcf acc+b4 rrcf acc+b5 infsnz exp ; test for floating point overflow goto setfov32 mul32ok btfss sign,msb bcf acc+b3,msb ; clear explicit msb if positive movfp acc+b3,aarg+b0 ; move result to aarg movfp acc+b4,aarg+b1 movfp acc+b5,aarg+b2 retlw 0 setfov32 bsf fpflags,fov ; set floating point underflag btfss fpflags,sat ; test for saturation retlw 0xff ; return error code in wreg setf aexp ; saturate to largest floating setf aarg+b0 ; point number = 0x ff 7f ff ff setf aarg+b1 ; modulo the appropriate sign bit setf aarg+b2 rlcf sign rrcf aarg+b0 retlw 0xff ; return error code in wreg 5-77 www.datasheet.co.kr datasheet pdf - http://www..net/ ds00575a-page 68 ? 1994 microchip technology inc. ieee 754 compliant floating-point routines ;********************************************************************************************** ;********************************************************************************************** ; floating point divide ; input: 32 bit floating point dividend in aexp, aarg+b0, aarg+b1, aarg+b2 ; 32 bit floating point divisor in bexp, barg+b0, barg+b1, barg+b2 ; use: call fpd32 ; output: 32 bit floating point quotient in aexp, aarg+b0, aarg+b1, aarg+b2 ; result: aarg < aarg / barg ; max timing: 27+11+548+11 = 597 clks rnd = 0 ; 27+11+548+35 = 621 clks rnd = 1, sat = 0 ; 27+11+548+41 = 627 clks rnd = 1, sat = 1 ; min timing: 6+6 = 12 clks aarg = 0 ; 33+428+11 = 472 clks ; pm: 42+572+47 = 661 dm: 14 div24 macro ; timing: 1+24*26 = 625 clks variable i = 0 bcf _c while i < 24 clrf temp ; left shift rlcf acc+b5 rlcf acc+b4 rlcf acc+b3 rlcf acc+b2 rlcf acc+b1 rlcf acc+b0 rlcf temp movfp barg+b2,wreg ; subtract subwf acc+b2 movfp barg+b1,wreg subwfb acc+b1 movfp barg+b0,wreg subwfb acc+b0 clrf wreg subwfb temp btfss _c ; test for restore goto drest#v( i ) bsf acc+b5,lsb goto dok#v( i ) drest#v( i ) movfp barg+b2,wreg ; restore if necessary addwf acc+b2 movfp barg+b1,wreg addwfc acc+b1 movfp barg+b0,wreg addwfc acc+b0 bcf acc+b5,lsb dok#v( i ) i += 1 5-78 www.datasheet.co.kr datasheet pdf - http://www..net/ ? 1994 microchip technology inc. ds00575a-page 69 ieee 754 compliant floating-point routines 5 endw endm div24a macro ; min timing: 19+23*23 = 548 clks ; min timing: 14+23*18 = 428 clks ; pm: 20+23*24 = 572 dm: 9 btg temp,lsb ; save carry movfp barg+b2,wreg ; subtract subwf acc+b2 movfp barg+b1,wreg subwfb acc+b1 movfp barg+b0,wreg subwfb acc+b0 rlcf wreg iorwf temp btfss temp,lsb ; test for restore goto darest0 bsf acc+b3,msb goto daok0 darest0 movfp barg+b2,wreg ; restore if necessary addwf acc+b2 movfp barg+b1,wreg addwfc acc+b1 movfp barg+b0,wreg addwfc acc+b0 bcf acc+b3,msb daok0 variable i = 1 while i < 24 bcf _c rlcf acc+b2 rlcf acc+b1 rlcf acc+b0 rlcf temp ; save carry movfp barg+b2,wreg ; subtract subwf acc+b2 movfp barg+b1,wreg subwfb acc+b1 movfp barg+b0,wreg subwfb acc+b0 rlcf wreg iorwf temp btfss temp,lsb ; test for restore goto darest#v( i ) if i < 8 bsf acc+b3,msb-i ; set bit in quotient endif 5-79 www.datasheet.co.kr datasheet pdf - http://www..net/ ds00575a-page 70 ? 1994 microchip technology inc. ieee 754 compliant floating-point routines if i >= 8 && i < 16 bsf acc+b4,15-i ; set bit in quotient endif if i >= 16 bsf acc+b5,23-i ; set bit in quotient endif goto daok#v( i ) darest#v( i ) movfp barg+b2,wreg ; restore if necessary addwf acc+b2 movfp barg+b1,wreg addwfc acc+b1 movfp barg+b0,wreg addwfc acc+b0 if i < 8 bcf acc+b3,msb-i ; clear bit in quotient endif if i >= 8 && i < 16 bcf acc+b4,15-i ; clear bit in quotient endif if i >= 16 bcf acc+b5,23-i ; clear bit in quotient endif daok#v( i ) i += 1 endw endm fpd32 clrf temp,w cpfsgt bexp ; test for divide by zero goto setfdz32 cpfsgt aexp goto res032 d32bne0 movfp aarg+b0,wreg xorwf barg+b0,w movpf wreg,sign ; save sign in sign bsf aarg+b0,msb ; make argument msbs explicit bsf barg+b0,msb talign32 incf temp ; set align increment movfp aarg+b0,acc+b3 ; test for alignment movfp aarg+b1,acc+b4 movfp aarg+b2,acc+b5 movfp barg+b2,wreg subwf acc+b5 movfp barg+b1,wreg subwfb acc+b4 5-80 www.datasheet.co.kr datasheet pdf - http://www..net/ ? 1994 microchip technology inc. ds00575a-page 71 ieee 754 compliant floating-point routines 5 movfp barg+b0,wreg subwfb acc+b3 btfsc _c goto dalign32ok bcf _c ; align if necessary rlcf acc+b2 rlcf acc+b1 rlcf acc+b0 decf temp ; fix align increment dalign32ok movfp bexp,wreg ; compute aexp - bexp subwf exp btfss _c goto altb32 ageb32 movlw expbias ; if aexp > bexp, test for addwf temp,w ; overflow addwf exp btfsc _c goto setfov32 goto dargok32 altb32 movlw expbias ; if aexp < bexp, test for addwf temp,w ; underflow addwf exp btfss _c goto setfun32 dargok32 div24a ; macro for division dround32 btfsc fpflags,rnd btfss acc+b5,lsb goto div32ok bcf _c ; compute next significant bit rlcf acc+b2 ; for rounding rlcf acc+b1 rlcf acc+b0 rlcf temp ; save carry movfp barg+b2,wreg ; subtract subwf acc+b2 movfp barg+b1,wreg subwfb acc+b1 movfp barg+b0,wreg subwfb acc+b0 rlcf wreg iorwf temp rrcf temp ; rotate next significant bit into clrf wreg ; carry and add for rounding addwfc acc+b5 addwfc acc+b4 addwfc acc+b3 btfss _c ; test if rounding caused carryout goto div32ok rrcf acc+b3 rrcf acc+b4 rrcf acc+b5 infsnz exp ; test for overflow goto setfov32 div32ok btfss sign,msb bcf acc+b3,msb ; clear explicit msb if positive movfp acc+b3,aarg+b0 ; move result to aarg movfp acc+b4,aarg+b1 movfp acc+b5,aarg+b2 5-81 www.datasheet.co.kr datasheet pdf - http://www..net/ ds00575a-page 72 ? 1994 microchip technology inc. ieee 754 compliant floating-point routines retlw 0 setfun32 bsf fpflags,fun ; set floating point underflag btfss fpflags,sat ; test for saturation retlw 0xff ; return error code in wreg movlw 0x01 ; saturate to smallest floating movpf wreg,aexp ; point number = 0x 01 00 00 00 clrf aarg+b0 ; modulo the appropriate sign bit clrf aarg+b1 clrf aarg+b2 rlcf sign rrcf aarg+b0 retlw 0xff ; return error code in wreg setfdz32 bsf fpflags,fdz ; set floating point divide by zero retlw 0xff ; flag and return error code in wreg ;********************************************************************************************** ;********************************************************************************************** ; floating point subtract ; input: 32 bit floating point number in aexp, aarg+b0, aarg+b1, aarg+b2 ; 32 bit floating point number in bexp, barg+b0, barg+b1, barg+b2 ; use: call fps32 ; output: 32 bit floating point difference in aexp, aarg+b0, aarg+b1, aarg+b2 ; result: aarg < aarg - barg ; max timing: 1+144 = 145 clks rnd = 0 ; 1+159 = 160 clks rnd = 1 ; min timing: 1+34 = 35 clks ; pm: 330 dm: 14 fps32 btg barg+b0,msb ; toggle sign bit for subtraction ; ; floating point add ; input: 32 bit floating point number in aexp, aarg+b0, aarg+b1, aarg+b2 ; 32 bit floating point number in bexp, barg+b0, barg+b1, barg+b2 ; use: call fpa32 ; output: 32 bit floating point sum in aexp, aarg+b0, aarg+b1, aarg+b2 ; result: aarg < aarg - barg ; max timing: 7+67+22+48 = 144 clks rnd = 0 ; 7+75+22+55 = 159 clks rnd = 1 ; min timing: 6+23+5 = 34 clks ; pm: 329 dm: 14 fpa32 movfp aarg+b0,wreg ; exclusive or of signs in temp xorwf barg+b0,w movpf wreg,temp movfp aexp,wreg ; use aarg if aexp >= bexp cpfsgt bexp goto usea32 5-82 www.datasheet.co.kr datasheet pdf - http://www..net/ ? 1994 microchip technology inc. ds00575a-page 73 ieee 754 compliant floating-point routines 5 useb32 movfp barg+b0,sign ; save sign in sign bsf barg+b0,msb ; make msbs explicit bsf aarg+b0,msb movfp aexp,wreg ; compute shift count in bexp movfp bexp,aexp subwf bexp btfsc _z goto bligned32 movlw 7 cpfsgt bexp ; do byte shift if bexp >= 8 goto bnib32 subwf bexp ; bexp = bexp - 7 rlcf aarg+b2 ; rotate next bit for rounding movfp aarg+b1,aarg+b2 movfp aarg+b0,aarg+b1 clrf aarg+b0 dcfsnz bexp ; bexp = bexp - 1 goto bround32 cpfsgt bexp ; do another byte shift if bexp >= 8 goto bnib32a subwf aexp ; bexp = bexp - 7 rlcf aarg+b2 ; rotate next bit for rounding movfp aarg+b1,aarg+b2 clrf aarg+b1 dcfsnz bexp ; bexp = bexp - 1 goto bround32 cpfsgt bexp ; if bexp still >= 8, then goto bnib32b ; aarg = 0 relative to barg movfp sign,aarg+b0 ; return barg movfp barg+b1,aarg+b1 movfp barg+b2,aarg+b2 retlw 0x00 bnib32b movlw 3 ; do nibbleshift if bexp >= 4 cpfsgt bexp goto bloop32b subwf bexp ; bexp = bexp -3 swapf aarg+b2,w movpf wreg,acc+b5 ; save for rounding andlw 0x0f movpf wreg,aarg+b2 rlcf acc+b5 ; rotate next bit for rounding dcfsnz bexp ; bexp = bexp - 1 goto bround32 ; aligned if bexp = 0 bloop32b bcf _c ; right shift by bexp rrcf aarg+b2 dcfsnz bexp goto bround32 ; aligned if bexp = 0 bcf _c rrcf aarg+b2 dcfsnz bexp goto bround32 ; aligned if bexp = 0 bcf _c ; at most 3 right shifts are rrcf aarg+b2 ; possible goto bround32 bnib32a movlw 3 ; do nibbleshift if bexp >= 4 cpfsgt bexp goto bloop32a subwf bexp ; bexp = bexp -3 5-83 www.datasheet.co.kr datasheet pdf - http://www..net/ ds00575a-page 74 ? 1994 microchip technology inc. ieee 754 compliant floating-point routines swapf aarg+b2,w movpf wreg,acc+b5 ; save for rounding andlw 0x0f movpf wreg,aarg+b2 swapf aarg+b1,w andlw 0xf0 addwf aarg+b2 swapf aarg+b1,w andlw 0x0f movpf wreg,aarg+b1 rlcf acc+b5 ; rotate next bit for rounding dcfsnz bexp ; bexp = bexp - 1 goto bround32 ; aligned if bexp = 0 bloop32a bcf _c ; right shift by bexp rrcf aarg+b1 rrcf aarg+b2 dcfsnz bexp goto bround32 ; aligned if bexp = 0 bcf _c rrcf aarg+b1 rrcf aarg+b2 dcfsnz bexp goto bround32 ; aligned if bexp = 0 bcf _c ; at most 3 right shifts are rrcf aarg+b1 ; possible rrcf aarg+b2 goto bround32 bnib32 movlw 3 ; do nibbleshift if bexp >= 4 cpfsgt bexp goto bloop32 subwf bexp ; bexp = bexp -3 swapf aarg+b2,w movpf wreg,acc+b5 ; save for rounding andlw 0x0f movpf wreg,aarg+b2 swapf aarg+b1,w andlw 0xf0 addwf aarg+b2 swapf aarg+b1,w andlw 0x0f movpf wreg,aarg+b1 swapf aarg+b0,w andlw 0xf0 addwf aarg+b1 swapf aarg+b0,w andlw 0x0f movpf wreg,aarg+b0 rlcf acc+b5 ; rotate next bit for rounding dcfsnz bexp ; bexp = bexp - 1 goto bround32 ; aligned if bexp = 0 bloop32 bcf _c ; right shift by bexp rrcf aarg+b0 rrcf aarg+b1 rrcf aarg+b2 5-84 www.datasheet.co.kr datasheet pdf - http://www..net/ ? 1994 microchip technology inc. ds00575a-page 75 ieee 754 compliant floating-point routines 5 dcfsnz bexp goto bround32 ; aligned if bexp = 0 bcf _c rrcf aarg+b0 rrcf aarg+b1 rrcf aarg+b2 dcfsnz bexp goto bround32 ; aligned if bexp = 0 bcf _c ; at most 3 right shifts are rrcf aarg+b0 ; possible rrcf aarg+b1 rrcf aarg+b2 bround32 btfsc fpflags,rnd btfss aarg+b2,lsb goto bligned32 clrf wreg addwfc aarg+b2 ; add carry for rounding addwfc aarg+b1 addwfc aarg+b0 btfss _c ; has rounding caused carryout? goto bligned32 rrcf aarg+b0 ; if so, right shift rrcf aarg+b1 rrcf aarg+b2 infsnz exp ; test for floating point overflow goto setfov32 bligned32 btfss temp,msb ; negate if signs opposite goto aok32 clrf wreg comf aarg+b2 comf aarg+b1 comf aarg+b0 incf aarg+b2 addwfc aarg+b1 addwfc aarg+b0 goto aok32 usea32 movfp aarg+b0,sign ; save sign in sign bsf aarg+b0,msb ; make msbs explicit bsf barg+b0,msb movfp bexp,wreg ; compute shift count in bexp subwf aexp,w movpf wreg,bexp btfsc _z goto aligned32 movlw 7 cpfsgt bexp ; do byte shift if bexp >= 8 goto anib32 subwf bexp ; bexp = bexp - 7 rlcf barg+b2 ; rotate next bit for rounding movfp barg+b1,wreg movpf wreg,barg+b2 movfp barg+b0,wreg movpf wreg,barg+b1 clrf barg+b0 dcfsnz bexp ; bexp = bexp - 1 goto around32 cpfsgt bexp ; do another byte shift if bexp >= 8 goto anib32a subwf bexp ; bexp = bexp - 7 rlcf barg+b2 ; rotate next bit for rounding movfp barg+b1,wreg movpf wreg,barg+b2 5-85 www.datasheet.co.kr datasheet pdf - http://www..net/ ds00575a-page 76 ? 1994 microchip technology inc. ieee 754 compliant floating-point routines clrf barg+b1 dcfsnz bexp ; bexp = bexp - 1 goto around32 cpfsgt bexp ; if bexp still >= 8, then goto anib32b ; barg = 0 relative to aarg movfp sign,aarg+b0 ; return aarg retlw 0x00 anib32b movlw 3 ; do nibbleshift if bexp >= 4 cpfsgt bexp goto aloop32b subwf bexp ; bexp = bexp -3 swapf barg+b2,w movpf wreg,acc+b5 ; save for rounding andlw 0x0f movpf wreg,barg+b2 rlcf acc+b5 ; rotate next bit for rounding dcfsnz bexp ; bexp = bexp - 1 goto around32 ; aligned if bexp = 0 aloop32b bcf _c ; right shift by bexp rrcf barg+b2 dcfsnz bexp goto around32 ; aligned if bexp = 0 bcf _c rrcf barg+b2 dcfsnz bexp goto around32 ; aligned if bexp = 0 bcf _c ; at most 3 right shifts are rrcf barg+b2 ; possible goto around32 anib32a movlw 3 ; do nibbleshift if bexp >= 4 cpfsgt bexp goto aloop32a subwf bexp ; bexp = bexp -3 swapf barg+b2,w movpf wreg,acc+b5 ; save for rounding andlw 0x0f movpf wreg,barg+b2 swapf barg+b1,w andlw 0xf0 addwf barg+b2 swapf barg+b1,w andlw 0x0f movpf wreg,barg+b1 rlcf acc+b5 ; rotate next bit for rounding dcfsnz bexp ; bexp = bexp - 1 goto around32 ; aligned if bexp = 0 aloop32a bcf _c ; right shift by bexp rrcf barg+b1 rrcf barg+b2 dcfsnz bexp goto around32 ; aligned if bexp = 0 bcf _c rrcf barg+b1 rrcf barg+b2 dcfsnz bexp goto around32 ; aligned if bexp = 0 5-86 www.datasheet.co.kr datasheet pdf - http://www..net/ ? 1994 microchip technology inc. ds00575a-page 77 ieee 754 compliant floating-point routines 5 bcf _c ; at most 3 right shifts are rrcf barg+b1 ; possible rrcf barg+b2 goto around32 anib32 movlw 3 ; do nibbleshift if bexp >= 4 cpfsgt bexp goto aloop32 subwf bexp ; bexp = bexp -3 swapf barg+b2,w movpf wreg,acc+b5 ; save for rounding andlw 0x0f movpf wreg,barg+b2 swapf barg+b1,w andlw 0xf0 addwf barg+b2 swapf barg+b1,w andlw 0x0f movpf wreg,barg+b1 swapf barg+b0,w andlw 0xf0 addwf barg+b1 swapf barg+b0,w andlw 0x0f movpf wreg,barg+b0 rlcf acc+b5 ; rotate next bit for rounding dcfsnz bexp ; bexp = bexp - 1 goto around32 ; aligned if bexp = 0 aloop32 bcf _c ; right shift by bexp rrcf barg+b0 rrcf barg+b1 rrcf barg+b2 dcfsnz bexp goto around32 ; aligned if bexp = 0 bcf _c rrcf barg+b0 rrcf barg+b1 rrcf barg+b2 dcfsnz bexp goto around32 ; aligned if bexp = 0 bcf _c ; at most 3 right shifts are rrcf barg+b0 ; possible rrcf barg+b1 rrcf barg+b2 around32 btfsc fpflags,rnd btfss barg+b2,lsb goto aligned32 clrf wreg addwfc barg+b2 ; add carry for rounding addwfc barg+b1 addwfc barg+b0 btfss _c ; has rounding caused carryout? goto aligned32 rrcf barg+b0 ; if so, right shift rrcf barg+b1 rrcf barg+b2 infsnz exp ; test for floating point overflow goto setfov32 5-87 www.datasheet.co.kr datasheet pdf - http://www..net/ ds00575a-page 78 ? 1994 microchip technology inc. ieee 754 compliant floating-point routines aligned32 btfss temp,msb ; negate if signs opposite goto aok32 clrf wreg comf barg+b2 comf barg+b1 comf barg+b0 incf barg+b2 addwfc barg+b1 addwfc barg+b0 aok32 movfp barg+b2,wreg ; add addwf aarg+b2 movfp barg+b1,wreg addwfc aarg+b1 movfp barg+b0,wreg addwfc aarg+b0 btfsc temp,msb goto acomp32 btfss _c goto fixsign32 rrcf aarg+b0 ; shift right and increment exp rrcf aarg+b1 rrcf aarg+b2 incfsz aexp goto fixsign32 goto setfov32 ; set floating point overflow flag acomp32 btfsc _c goto nrm32 ; normalize and fix sign clrf wreg ; negate, toggle sign bit and comf aarg+b2 ; then normalize comf aarg+b1 comf aarg+b0 incf aarg+b2 addwfc aarg+b1 addwfc aarg+b0 btg sign,msb goto nrm32 end 5-88 www.datasheet.co.kr datasheet pdf - http://www..net/ w orldwide s ales & s ervice americas (continued) san jose microchip technology inc. 2107 north first street, suite 590 san jose, ca 95131 tel: 408 436-7950 fax: 408 436-7955 asia/pacific hong kong microchip technology unit no. 3002-3004, tower 1 metroplaza 223 hing fong road kwai fong, n.t. hong kong tel: 852 2 401 1200 fax: 852 2 401 3431 korea microchip technology 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku, seoul, korea tel: 82 2 554 7200 fax: 82 2 558 5934 singapore microchip technology 200 middle road #10-03 prime centre singapore 188980 tel: 65 334 8870 fax: 65 334 8850 taiwan microchip technology 10f-1c 207 tung hua north road taipei, taiwan, roc tel: 886 2 717 7175 fax: 886 2 545 0139 europe united kingdom arizona microchip technology ltd. unit 6, the courtyard meadow bank, furlong road bourne end, buckinghamshire sl8 5aj tel: 44 0 1628 851077 fax: 44 0 1628 850259 france arizona microchip technology sarl 2 rue du buisson aux fraises 91300 massy - france tel: 33 1 69 53 63 20 fax: 33 1 69 30 90 79 germany arizona microchip technology gmbh gustav-heinemann-ring 125 d-81739 muenchen, germany tel: 49 89 627 144 0 fax: 49 89 627 144 44 italy arizona microchip technology srl centro direzionale colleoni palazzo pegaso ingresso no. 2 via paracelso 23, 20041 agrate brianza (mi) italy tel: 39 039 689 9939 fax: 39 039 689 9883 japan microchip technology intl. inc. benex s-1 6f 3-18-20, shin yokohama kohoku-ku, yokohama kanagawa 222 japan tel: 81 45 471 6166 fax: 81 45 471 6122 9/22/95 americas corporate of ce microchip technology inc. 2355 west chandler blvd. chandler, az 85224-6199 tel: 602 786-7200 fax: 602 786-7277 technical support: 602 786-7627 web: http://www.mchip.com/microhip atlanta microchip technology inc. 500 sugar mill road, suite 200b atlanta, ga 30350 tel: 770 640-0034 fax: 770 640-0307 boston microchip technology inc. 5 mount royal avenue marlborough, ma 01752 tel: 508 480-9990 fax: 508 480-8575 chicago microchip technology inc. 333 pierce road, suite 180 itasca, il 60143 tel: 708 285-0071 fax: 708 285-0075 dallas microchip technology inc. 14651 dallas parkway, suite 816 dallas, tx 75240-8809 tel: 214 991-7177 fax: 214 991-8588 dayton microchip technology inc. 35 rockridge road englewood, oh 45322 tel: 513 832-2543 fax: 513 832-2841 los angeles microchip technology inc. 18201 von karman, suite 455 irvine, ca 92715 tel: 714 263-1888 fax: 714 263-1338 new york microchip technology inc. 150 motor parkway, suite 416 hauppauge, ny 11788 tel: 516 273-5305 fax: 516 273-5335 information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. no representation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of microchip? products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, under any intellectual property rights. the microchip logo and name are registered trademarks of microchip technology inc. all rights reserved. all other trademarks mentioned herein are the property of their respective companies. all rights reserved. 1995, microchip technology incorporated, usa. www.datasheet.co.kr datasheet pdf - http://www..net/ |
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